AMBA Color LCD Controller Data Sheet


Table of Contents

1. AMBA Color LCD Controller
1.1. Module overview
1.2. Display Specifications
1.3. AMBA Signal Descriptions
1.3.1. Address and Control Signal Timing
1.4. ASB Bus Master
1.4.1. Bus Master Interface Description
1.4.2. Bus Master Timing Diagrams
1.4.3. Timing Parameters
1.5. LCD Controller Operation
1.5.1. DMA to Memory (AMBA) Interface
1.5.2. Frame Buffer
1.5.3. Input FIFO
1.5.4. Look Up Palette
1.5.5. Color/grayscale Dithering
1.5.6. Output FIFO
1.5.7. LCD controller Pins
1.6. LCD Controller Register Definitions
1.7. LCD Control Register
1.7.1. LCD Enable (LcdEn)
1.7.2. LCD Monochrome (LcdBW)
1.7.3. LCD Done Mask (DoneMask)
1.7.4. LCD Next Mask (Next Mask)
1.7.5. LCD Error Mask (Error Mask)
1.7.6. LCD TFT (LcdTFT)
1.7.7. LCD Big Endian (LcdBE)
1.7.8. Mono 8 Bit Mode (M8B)
1.7.9. 1.7.10 FIFO DMA Request Delay (FDD)
1.8. LCD Timing 0 Register
1.8.1. Pixels-per-line (PPL)
1.8.2. Horizontal Sync Pulse Width (HSW)
1.8.3. Horizontal Front Porch (HFP)
1.8.4. Horizontal Back Porch (HBP)
1.9. LCD Timing 1 Register
1.9.1. Lines Per Panel (LPP)
1.9.2. Vertical Sync Pulse Width (VSW)
1.9.3. Vertical Front Porch (VFP)
1.9.4. Vertical Back Porch (VBP)
1.10. LCD Timing 2 Register
1.10.1. Pixel Clock Divider (PCD)
1.10.2. AC-bias Pin Frequency (ACB)
1.10.3. AC-bias Line Transitions Per Interrupt (ACBI)
1.10.4. Invert Vsync (IVS)
1.10.5. Invert Hsync (IHS)
1.10.6. Invert Pixel Clock (IPC)
1.10.7. Invert Output Enable (IEO)
1.11. LCD Controller DMA Registers
1.12. DMA Channel 1 Base Address Register
1.13. DMA Channel 1 Current Address Register
1.14. DMA Channel 2 Base and Current Address Registers
1.15. LCD Controller Status Register
1.15.1. Frame Done (Done) (read-only)
1.15.2. Next Frame (Next) (read-only)
1.15.3. Bus Error Status (BER) (read/write)
1.15.4. AC Bias Count Status (ABC) (read/write)
1.15.5. FIFO Underflow Status (FUF) (read/write)
1.16. Gray Scaler Test Read Frame Phase Register
1.17. Gray Scaler Test Read Row Phase Register
1.18. Gray Scaler Test Read Column Phase Register
1.19. Upper Panel Palette Test Read
1.20. Lower Panel Palette Test Read
1.21. Gray Scaler Test Write
1.22. LCD Controller Register Locations

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Product Status

The information in this document is final, that is for a developed product.

Revision History
Revision AAugust 1997First issue
Revision BSeptember 1997Corrections to equations on pages 19 and 35
Revision CDecember 1997Minor amendments
Revision DJune 1998Minor amendments
Copyright © 1997, 1998 ARM Limited. All rights reserved.ARM DDI 0121D
Non-Confidential