Each ASB slave, ASB master and APB peripheral should be tested in complete isolation. This means that components must be designed with test veneers that allow non-bus signals to be controlled and observed. When a component is tested, a special test bit is set. This test bit switches these multiplexed signals to test registers (accessible via the ASB), which effectively isolates each component from the rest of the system. Test vectors should be written to test the component in isolation, making as few assumptions about the rest of the system as possible.

A good example of this approach is provided by the test veneer for the ARM processor, which is described in the AMBA ARM7TDMI Interface Data Sheet. This approach is also used to test the peripherals on the APB bus.

Under normal conditions, when the TIC is not in use, the current bus master performs transfers to and from any one of the following slaves:

However, when test mode is entered, and the TIC is the current master, the following slaves can be accessed:

The EBI cannot be tested via the TIC because of the way test access is provided to the ASB bus. The TIC is a state machine driven by the test request inputs (TREQA and TREQB). It also contains a latch that allows it to read address information from the test bus (TBUS) and drive it onto BA. However, it cannot drive BD. Instead, it overrides the normal function of the EBI, forcing it to provide a 32-bit, bidirectional channel between TBUS and BD. Thus in test mode the EBI cannot function as a slave.

TBUS must be a 32-bit channel. Thus in a system which only supports a 16-bit or 8-bit external data bus, additional external pins such as external address lines must be forced into a special test mode in order to supply the full 32-bit bidirectional channel required.

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