In normal operation (not in system test mode), to perform a read from the external memory, the XnGBE signal must be LOW, to enable driving of the address and data buses (XA and XD). The latched address (taken from BA) is driven onto XA. If XOEN is LOW (indicating a read) XD is driven to a high impedance, to allow the read data to be applied.

Figure 3.29 shows the timing of a read from memory with zero wait states. Note that the data must be valid on the XD bus in time for the signal to propagate on-chip so that the BD bus becomes valid before the next falling edge of BCLK. If this setup time cannot be achieved, the access will require wait states.

To perform a write to the external memory, XOEN must be HIGH, to allow XD to be driven by the SMI with a latched version of BD.

The SMI requires at least one wait state to be added for a write to memory, to allow for the timing of the XWEN write enable signal relative to the XA and XD buses. When XWEN is LOW, XA must be stable, and on the rising edge of XWEN, XD must be valid.

Figure 3.30, shows the timing of a write to memory with a single wait state.

The XCSN chip select lines are controlled by the values of BA, Remap, and DSELExtMem. A falling edge registered version of DSELExtMem is used, and a latched version of BA is used (transparent when BCLK is LOW), so XCSN is effectively generated on the falling edge of BCLK.

Table 3‑8 on page 3‑53 shows the relationship between the three inputs and the generated value of XCSN.

XCSN[7:0] is also held in the "11111111" state asynchronously during reset.

The 4-bit XWEN write enable signal allows the four bytes in the 32-bit wide word to be written independently. The byte assignments are:

The SMI controls XWEN for writes in word (32-bit), halfword (16-bit) and byte quantities. The SMI uses BSIZE[1:0] and BA[1:0] to select the width and order of each write to memory. This information must be valid before XWEN is asserted.

Table 3‑9 on page 3‑54 shows the bytes selected according to the BSIZE and BA[1:0] inputs.

The SMI only supports global (the same for every bank) wait states for read and write accesses. This is configurable (in the HDL model, not in synthesized hardware) between zero and three waits for reads, and between one and three for writes. Figure 3.30 shows a memory transfer with one wait state. A transfer with more wait states causes further wait cycles. The address and data information remains valid until the access cycle is completed. For writes, the XWEN signal is extended, going LOW during the first wait, and not going HIGH until the final cycle of the transfer. Before synthesis, the wait states can be selected by altering the 2-bit wide constants READWAIT and WRITEWAIT. WRITEWAIT must be value 01 or greater. The SMI also allows transfer wait to be extended indefinitely. This is done by asserting XWAIT HIGH. To wait the current transfer, XWAIT must be asserted before the rising edge of BCLK in the last waited cycle of the access.

The transfer cannot complete until XWAIT is LOW for at least one cycle.

During system test the SMI is controlled by three active LOW signals from the TIC:

For more information on system test, refer to the AMBA Specification. For the SMI, BCLK is used as TCLK, and XD as TBUS. The TIC signals control the data bus drivers and the latch directly. It is necessary to override the normal operation of the interface when in test mode. This is done with the TestMode signal from the TIC.