4.1.5. Interrupt registers standard configuration
The FIQ interrupt controller is one bit wide and is located
on bit 0. The source of this interrupt is implementation dependent.
The interrupt controller will be customized to fit into each
application. The following is an example minimum set of interrupt
bits assigned in a system.
Bits 1 to 5 in the IRQ interrupt controller are defined in
the standard EASY world. Bit 0 and Bits 6 up to 31 are available
for use as required. Bit 0 is left available so that the FIQ source
may also be routed to the IRQ controller in an identical bit position.
Table 4.3. Example of IRQ sources
Bit | Interrupt Source |
|---|
0 | |
1 | Programmed Interrupt |
2 | Comms Rx |
3 | Comms Tx |
4 | Timer 1 |
5 | Timer 2 |
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