ASB Example AMBA ™ SYstem TechnicalReference Manual


Table of Contents

Preface
About this manual
Using this manual
Conventions
Additional reading
Feedback
Feedback on this product
Feedback on this manual
1. Introduction
1.1. Overview
1.1.1. EASY system blocks
1.1.2. EASY components
2. Microcontroller
2.1. Functional overview
2.2. The AMBA system components
2.2.1. Reset controller
2.2.2. Arbiter
2.2.3. Decoder
2.2.4. ASB to APB bridge
2.3. Reference peripherals
2.3.1. Timer
2.3.2. Interrupt controller
2.3.3. Remap and pause controller
2.4. Example components
2.4.1. Internal memory
2.4.2. Static memory interface
2.5. System test methodology
3. ASB Modules
3.1. APB bridge
3.1.1. Hardware interface and signal description
3.1.2. Peripheral memory map
3.1.3. Function and operation of block
3.1.4. System description
3.2. Arbiter
3.2.1. Signal descriptions
3.2.2. Abitration process
3.2.3. Signal timing
3.2.4. Arbitration priorities
3.2.5. System description
3.3. Decoder
3.3.1. Overview
3.3.2. Signal description
3.3.3. Memory map
3.3.4. Function and operation of block
3.3.5. System description
3.4. Reset controller
3.4.1. Signal timing
3.4.2. Use of BnRES
3.4.3. Bus reset state machine
3.4.4. System description
3.5. Static memory interface
3.5.1. Functional description
3.5.2. System description
3.6. Example system external memory
3.6.1. Memory devices
3.6.2. Memory connection
3.7. Test interface controller
3.7.1. Functional description
3.8. AMBA ARM7TDMI interface
3.8.1. Signal description
3.8.2. Overview of the wrapper blocks
3.8.3. Default signal configurations
3.8.4. Description of the wrapper blocks
3.8.5. Removal of the test interface
4. APB Modules
4.1. Interrupt controller
4.1.1. Hardware interface and signal description
4.1.2. Interrupt controller
4.1.3. Interrupt controller memory map
4.1.4. Interrupt controller register descriptions
4.1.5. Interrupt registers standard configuration
4.1.6. System description
4.2. Remap and pause controller
4.2.1. Hardware interface and signal description
4.2.2. Remap and pause
4.2.3. Remap and pause memory map
4.2.4. Remap and pause register descriptions
4.2.5. System description
4.3. Timer
4.3.1. Hardware interface and signal description
4.3.2. Timer introduction
4.3.3. Timer operation
4.3.4. Timer memory map
4.3.5. Timer register descriptions
4.3.6. Test register
4.3.7. System description
4.3.8. FRC system description
5. Test Interface Driver
5.1. Introduction
5.2. TICBOX usage
5.3. TICTalk command language
5.3.1. TICTalk commands
5.3.2. Programming with TICTalk commands
5.3.3. The TICTalk file
5.3.4. Generating a test input file format
5.3.5. TIF format
6. Designer’s Guide
6.1. Adding bus masters
6.1.1. Arbiter modifications
6.1.2. Bus master requirements
6.2. Adding ASB slaves
6.2.1. Decoder modifications
6.2.2. Slave requirements
6.3. Adding APB peripherals
6.3.1. APB bridge modifications
6.3.2. Peripheral requirements
6.4. Choosing a decoder implementation
6.4.1. Decoder with decode cycles
6.4.2. Decoder without decode cycles

List of Figures

1. Key to timing diagram conventions
1.1. EASY system diagram
2.1. The role of the decoder in the AMBA bus
2.2. Block diagram of the RPS block and bridge
2.3. Simple test veneer example
3.1. Block diagram of bridge module
3.2. APB write cycle
3.3. APB read cycle
3.4. APB burst cycle
3.5. Peripheral memory map
3.6. State machine for APB controller
3.7. APB bridge module block diagram
3.8. APB bridge module system diagram
3.9. Arbiter block diagram
3.10. Arbitration timing
3.11. Arbitration timing with BLOK set andturnaround cycle
3.12. Arbiter module block diagram
3.13. Arbiter module system diagram
3.14. Decoder block diagram
3.15. Memory map
3.16. Decoder with decode cycles
3.17. Decoder without decode cycles
3.18. Decoder with decode cycles state machine
3.19. Decoder without decode cycles state machine
3.20. Decoder module block diagram
3.21. Decoder module system diagram
3.22. Reset controller block diagram
3.23. BnRES timing
3.24. State machine for reset controller
3.25. Reset controller module block diagram
3.26. Reset controller module system diagram
3.27. Delayed state change timing diagram
3.28. Static memory interface block diagram
3.29. Zero wait memory read
3.30. Memory write with one wait state
3.31. Static memory interface module blockdiagram
3.32. Static memory interface module systemdiagram
3.33. Test interface controller block diagram
3.34. State machine
3.35. TIC vectors and AMBA transfers
3.36. Vectors and waited transfers
3.37. Read vectors and turnaround
3.38. Block diagram for ARM7TDMI AMBA masterlogic
3.39. Main modules of the ARM7TDMI AMBA interface
3.40. Main test state machine state diagram
4.1. Interrupt controller module block diagram
4.2. Single bit slice of the interrupt controller
4.3. Interrupt controller module blockdiagram
4.4. Interrupt controller slice system diagram
4.5. Interrupt controller module systemdiagram
4.6. Remap and pause module block diagram
4.7. Remap and pause module block diagram
4.8. Remap and pause module system diagram
4.9. Pause signal timing
4.10. Timer module block diagram
4.11. Timer operation
4.12. Prescale unit
4.13. The control register
4.14. Timer module block diagram
4.15. Timer module system diagram
4.16. Timer module counter enable timing -system clock selected
4.17. Timer module counter enable timing -test clock selected
4.18. FRC module system diagram
4.19. FRC module decrement diagram
5.1. TICBOX connection to an AMBA system

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The product described in this document is subject to continuousdevelopments and improvements. All particulars of the product andits use contained in this document are given by ARM in good faith.However, all warranties implied or expressed, including but notlimited to implied warranties of merchantability, or fitness forpurpose, are excluded.

This document is intended only to assist the reader in theuse of the product. ARM Limited shall not be liable for any lossor damage arising from the use of any information in this document,or any error or omission in such information, or any incorrect useof the product.

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ConfidentialityStatus

This document is Non-Confidential. The right to use, copyand disclose this document may be subject to license restrictionsin accordance with the terms of the agreement entered into by ARMand the party that ARM delivered this document to.

Product Status

The information in this document is final, that is for a developedproduct.

Revision History
Revision A October1998 First release.
Revision B& C July 1999 Note: IssuesB and C were not released.
Revision D August1999 Name change to ASB EASY.
Copyright © 1998-1999 ARM Limited. All rights reserved. ARM DDI 0138D
Non-Confidential