ARM PrimeCell® Technical Reference Manual 1.1.1. Features of the PrimeCell UART

The PrimeCell UART offers:

Compliance to the AMBA Specification (Rev 2.0) onwards for easy integration into System-on-a-Chip (SoC) implementation.
Programmable use of PrimeCell UART or IrDA SIR input/output.
Separate 16-byte transmit and receive first-in, first-out memory buffers (FIFOs) to reduce CPU interrupts.
Programmable FIFO disabling for 1-byte depth.
Programmable baud rate generator. This allows division of reference clock by (2x16) to (65536x16) and generates an internal x16 clock.
Standard asynchronous communication bits (start, stop and parity). These are added prior to transmission and removed on reception.
Independent masking of transmit FIFO, receive FIFO, receive timeout and modem status interrupts.
False start bit detection.
Line break generation and detection.
Support of the modem control functions CTS, DCD, and DSR.
Fully-programmable serial interface characteristics:
- data can be 5, 6, 7 or 8 bits
- even, odd or no-parity bit generation and detection
- 1 or 2 stop bit generation
- baud rate generation, dc up to UARTCLK_max_freq/32.
IrDA SIR Endec block providing:
- programmable use of IrDA SIR or PrimeCell UART input/output
- support of IrDA SIR Endec functions for data rates up to 115.2Kbits/second half-duplex
- support of normal 3/16 and low-power (1.41–2.23μs) bit durations
- programmable internal clock generator allowing division of reference clock by 2 to 512 for low-power mode bit duration.

Figure 1.1 shows a block diagram of the PrimeCell UART.

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