ARM PrimeCell® Technical Reference Manual A.2. On-chip signals

A.2. On-chip signals

A free-running reference clock, UARTCLK, must be provided. By default it is assumed to be asynchronous to PCLK. The UARTCLK clock must have a frequency between 2.7MHz and 542.7MHz to ensure that the low-power mode transmit pulse duration complies with the IrDA SIR specification.

The reset inputs are asynchronously asserted but synchronously removed for each of the clock domains within the PrimeCell UART. This ensures that logic is reset even if clocks are not present, to avoid any static power consumption problems at power up. Each clock domain has a individual reset to simplify the process of inserting scan test cells.

The on-chip signals required in addition to the AMBA APB signals are shown in Table A.2.

Table A.2. On-chip signal descriptions

Name	Type	Source/ destination	Description
UARTCLK	Input	Clock generator	PrimeCell UART reference clock.
nUARTRST	Input	Reset controller	PrimeCell UART reset signal to UARTCLK clock domain, active LOW. The reset controller must use BnRES to assert nUARTRST asynchronously but negate it synchronously with UARTCLK.
UARTMSINTR	Output	Interrupt controller	PrimeCell UART modem status interrupt (active HIGH).
UARTRXINTR	Output	Interrupt controller	PrimeCell UART receive FIFO interrupt (active HIGH).
UARTTXINTR	Output	Interrupt controller	PrimeCell UART transmit FIFO interrupt (active HIGH).
UARTRTINTR	Output	Interrupt controller	PrimeCell UART receive Timeout interrupt (active HIGH).
UARTINTR	Output	Interrupt controller	PrimeCell UART interrupt (active HIGH). A single combined interrupt generated as an OR function of the four individually maskable interrupts above.
SCANMODE	Input	Test controller	PrimeCell UART scan test hold input. This signal must be asserted HIGH during scan testing to ensure that internal data storage elements can be asynchronously reset. SCANMODE must be negated LOW during normal use or when applying manufacturing test vectors via the TIC.

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