[7:4]

-

Reserved, read unpredictable, should be written as 0.

[3]

IrDA Low Power

Test Count Enable

(ILPTESTCOUNT)

Setting this bit to 1 enables the low-power test count enable mode (nibble mode). The test mode enables verification of counter functionality in less clock cycles, because the counter is decremented by 0x11 instead of 0x01 as in normal mode.

This bit is cleared to 0 for normal operation so that the counter decrements by 1 on each enabled clock cycle.

[2]

UART Baud Rate

Test Count Enable

(BRTESTCOUNT)

Setting this bit to 1 enables the baud rate counter test mode (nibble mode). The test mode enables verification of counter functionality in less clock cycles since the counter is decremented by 0x1111 instead of 0x0001 as in normal mode.

This bit is cleared to 0 for normal operation so that the counter decrements by 1 on each enabled clock cycle.

[1]

SIR Test Enable

(SIRTEST)

Setting this bit to 1 enables the receive data path during IrDA transmission (testing requires the SIR to be configured in full-duplex mode). This bit must be set to 1 to enable SIR system loopback testing, when the normal mode control register UARTCR bit 7,Loop Back Enable (LBE) has been set to 1.

Clearing this bit to 0 disables the receive logic when the SIR is transmitting (normal operation).

This bit defaults to 0 for normal operation (half-duplex operation).

[0]

UART Baud rate Counter

Test Bypass Enable

(BRCBYPASS)

Setting this bit to 1 makes the external clock input UARTCLK bypass the baud rate generator, as if it were now a x16 baud rate clock signal. This provides a divide-by-1 baud rate test mode for faster verification and testing, which only requires 16 cycles per bit.