The IrDA SIR Endec provides functionality which converts between an asynchronous PrimeCell UART data stream and half-duplex serial SIR interface. No analog processing is performed on-chip. The role of the SIR endec is only to provide a digital encoded output and decoded input to the PrimeCell UART. There are two modes of operation:

In both normal and low-power IrDA modes, during transmission, the PrimeCell UART data bit is used as the base for encoding, while during reception the decoded bits are transferred to the PrimeCell UART receive logic.

The IrDA SIR physical layer specifies a half duplex communication link with a minimum 10ms delay between transmission and reception. This delay must be generated by software since it is not supported by the PrimeCell UART. The delay is required since the Infrared receiver electronics may become biased or even saturated from the optical power coupled from the adjacent transmitter LED. This delay is known as latency or receiver setup time. Shorter delays may be able to be used when the link first starts up.

The IrLPBaud16 signal is generated by dividing down the UARTCLK signal according to the low-power divisor value written to UARTILPR.

The low-power divisor value is calculated as:

Low-power divisor = (FUARTCLK / FIrLPBaud16) –1

where FIrLPBaud16 is nominally 1.8432MHz.

The divisor must be chosen so that 1.42MHz < IrLPBaud16 < 2.12MHz.