The PrimeCell UART and IrDA SIR Endec are reset by the global reset signal BnRES and a block-specific reset signal nUARTRST. An external reset controller must use BnRES to assert nUARTRST asynchronously and negate it synchronously to UARTCLK. BnRES should be asserted LOW for a period long enough to reset the slowest block in the on-chip system, and then taken HIGH again. The PrimeCell UART requires BnRES to be asserted LOW for at least one period of PCLK.

The values of the registers after reset are detailed in Chapter 1 Introduction.