There are five interrupts generated by the PrimeCell UART. Four of these are individual maskable active HIGH interrupts:

The interrupts are also output as a combined single interrupt UARTINTR.

Each of the four individual maskable interrupts is enabled or disabled by changing the mask bits in UARTCR. Setting the appropriate mask bit HIGH enables the interrupt.

Provision of individual outputs as well as a combined interrupt output, allows use of either a global interrupt service routine, or modular device drivers to handle interrupts.

The transmit and receive dataflow interrupts UARTRXINTR and UARTTXINTR have been separated from the status interrupts. This allows UARTRXINTR and UARTTXINTR to be used in a DMA controller, so that data can be read or written in response to just the FIFO trigger levels.

The status of the individual interrupt sources can be read from UARTIIR.