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The PrimeCell GPIO test registers are memory-mapped as shown in Table 4.1.
Table 4.1. Test registers memory map
Address | Type | Width | Reset value | Name | Description |
|---|---|---|---|---|---|
GPIO Base + 0x40–0x7c | Read/write | 0 | - | GPIOTCER | Test clock enable register. |
GPIO Base + 0x80 | Read/write | 5 | 0x00 | GPIOTCR | Test control register. |
GPIO Base + 0x84 | Read/write | 8 | 0x00 | GPIOTISRA | Test input stimulus register for port A. |
GPIO Base + 0x88 | Read/write | 8 | 0x00 | GPIOTISRB | Test input stimulus register for port B. |
Each register shown in Table 4.1 is described below.
| Copyright © 1999 ARM Limited. All rights reserved. | ARM DDI0142B |
| Non-Confidential | |
| PDF version | |
| Home > Programmer’s Model for Test > Test registers |