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The PrimeCell GPIO registers are shown in Table 3.1.
Table 3.1. PrimeCell GPIO register summary
Address | Type | Width | Reset value | Name | Description |
|---|---|---|---|---|---|
GPIO Base + 0x00 | Read/write | 8 | 0x00 | GPIOPADR | Port A data register. |
GPIO Base + 0x04 | Read/write | 8 | 0x00 | GPIOPBDR | Port B data register. |
GPIO Base + 0x08 | Read/write | 8 | 0x00 | GPIOPADDR | Port A data direction register. |
GPIO Base + 0x0c | Read/write | 8 | 0x00 | GPIOPBDDR | Port B data direction register. |
GPIO Base + 0x10–0x3c | - | - | - | - | Reserved. |
GPIO Base + 0x40–0x88 | - | - | - | - | Reserved (for test purposes). |
GPIO Base + 0x8c–0xff | - | - | - | - | Reserved. |
| Copyright © 1999 ARM Limited. All rights reserved. | ARM DDI0142B |
| Non-Confidential | |
| PDF version | |
| Home > Programmer’s Model > Summary of PrimeCell GPIO registers |