KMISTG2 is the PrimeCell KMI stage 2 timer register. It is a read-only register that provides observability of the stage 2 counter of the 17‑bit timer. This counter stage is a 3-bit, free-running, up counter that operates on REFCLK. The counter reloads on overflow. In addition, this register provides visibility of the 64μs and 16ms time-out pulses. Table 4.8 shows the bit assignments for the KMISTG2 register.