ARM940T Technical Reference Manual

(Rev 2)

Table of Contents

About this document
Intended audience
Using this manual
Typographical conventions
Timing diagram conventions
Further reading
ARM publications
Other publications
Feedback on the ARM940T
Feedback on the ARM940T Technical Reference Manual
1. Introduction
1.1. About the ARM940T
1.2. Processor functional block diagram
2. Programmer’s Model
2.1. About the programmer’s model
2.2. About the ARM9TDMI programmer’s model
2.2.1. Data Abort model
2.2.2. Instruction set extension spaces
2.3. CP15 register map summary
2.3.1. Accessing CP15 registers
2.3.2. Register 0, ID code
2.3.3. Register 0, cache type
2.3.4. Register 1, control register
2.3.5. Register 2, instruction and data cachable registers
2.3.6. Register 3, write buffer control register
2.3.7. Register 4, reserved
2.3.8. Register 5, instruction and data space protection registers
2.3.9. Register 6, protection region base and size registers
2.3.10. Register 7, cache operations register
2.3.11. Register 8, reserved
2.3.12. Register 9, instruction and data lockdown registers
2.3.13. Registers 10 to 14, reserved
2.3.14. Register 15, test/debug register
3. Protection Unit
3.1. About the protection unit
3.2. Enabling the protection unit
3.3. Memory regions
3.3.1. Region base address
3.3.2. Region size
3.3.3. Partition attributes
3.4. Overlapping regions
3.4.1. Background regions
4. Caches and Write Buffer
4.1. Cache architecture
4.2. ICache
4.2.1. Enabling and disabling the ICache
4.2.2. ICache operation
4.2.3. ICache validity
4.3. DCache
4.3.1. Enabling and disabling the DCache
4.3.2. Operation of the GCd bit and GBd bit
4.3.3. DCache operation
4.3.4. DCache validity
4.3.5. DCache clean and flush
4.4. The write buffer
4.4.1. Write buffer operation
4.4.2. Enabling and disabling the write buffer
4.4.3. Buffered writes
4.4.4. Drain write buffer
4.5. Cache lockdown
4.5.1. Locking down the caches
5. Clock Modes
5.1. About ARM940T clocking
5.2. FastBus mode
5.3. Synchronous mode
5.4. Asynchronous mode
6. Bus Interface Unit
6.1. About the ARM940T bus interface
6.2. ASB transfers
6.2.1. Noncached LDRs and noncached fetches
6.2.2. Noncached LDM
6.2.3. Noncached LDM crossing a 4KB boundary
6.2.4. Buffered and nonbuffered STR
6.2.5. Buffered and nonbuffered STM
6.2.6. NCNB STM crossing a 4KB boundary
6.2.7. Cached LDR, cached LDM, and cached fetch
6.2.8. Dirty data eviction, write-back of 4 words
6.2.9. Swap
6.2.10. AMBA ASB slave transfers
6.3. External aborts
6.4. Memory access order
7. Coprocessor Interface
7.1. About the coprocessor interface
7.1.1. User-assignable coprocessor numbers
7.1.2. External coprocessors
7.2. LDC or STC
7.2.1. Coprocessor handshake encoding
7.3. MCR/MRC
7.4. Interlocked MCR
7.5. CDP
7.6. Privileged instructions
7.7. Busy-waiting and interrupts
8. Debug Support
8.1. About debug support
8.2. Debug systems
8.2.1. Debug host
8.2.2. Protocol converter
8.2.3. Debug target (ARM940T)
8.3. Debug interface signals
8.3.1. Entry into debug state on breakpoint
8.3.2. Breakpoints and exceptions
8.3.3. Watchpoints
8.3.4. Watchpoints and exceptions
8.3.5. Debug request
8.3.6. Actions of the ARM940T in debug state
8.4. Scan chains and JTAG interface
8.5. The JTAG state machine
8.5.1. Reset
8.5.2. Pull-up resistors
8.5.3. Instruction register
8.5.4. Public instructions
8.6. Test data registers
8.6.1. Bypass register
8.6.2. ARM940T device identification (ID) code register
8.6.3. Instruction register
8.6.4. Scan chain select register
8.6.5. Scan chains 0, 1, 2, 3, 4, 5, and 15
8.7. ARM940T core clocks
8.7.1. Clock switching during debug
8.7.2. Clock switching during test
8.8. Determining the core and system state
8.8.1. Determining the core state
8.8.2. Determining system state
8.8.3. Instructions that can have the SYSSPEED bit set
8.9. Exit from debug state
8.10. The behavior of the program counter during debug
8.10.1. Breakpoint
8.10.2. Watchpoint
8.10.3. Watchpoint with another exception
8.10.4. Watchpoint and breakpoint
8.10.5. Debug request
8.10.6. System speed accesses
8.10.7. Summary of return address calculations
8.11. EmbeddedICE unit
8.11.1. Register map
8.11.2. Using the mask register
8.11.3. Control registers
8.11.4. Debug control register
8.11.5. Debug status register
8.11.6. Vector catch register
8.12. Vector catching
8.13. Single-stepping
8.14. Debug communications channel
8.14.1. Debug comms channel registers
8.14.2. Communication using the comms channel
8.14.3. Software polling communication
8.14.4. Interrupt driven communications
8.15. The debugger view of the cache
8.15.1. Scan access to the CP15 registers
8.15.2. Scan access to the caches
9. TrackingICE
9.1. About TrackingICE
9.2. Timing requirements
9.3. TrackingICE outputs
10. Test Support
10.1. About test support
10.1.1. ARM9TDMI
10.1.2. ARM940T macrocell
10.2. Scan chain 0 bit order
11. Instruction Cycle Summary and Interlocks
11.1. About the instruction cycle summary
11.2. Instruction cycle times
11.2.1. Multiplier cycle counts
11.3. Interlocks
12. AC Characteristics
12.1. ARM940T timing diagrams
12.2. ARM940T timing parameters
A. ARM940T Signal Descriptions
A.1. AMBA signals
A.1.1. AMBA bus specification
A.2. Coprocessor interface signals
A.3. JTAG and TAP controller signals
A.4. Debug signals
A.5. Miscellaneous signals

List of Figures

1. Key to timing diagram conventions
1.1. ARM940T functional block diagram
2.1. CP15 MRC and MCR bit pattern
2.2. Cache type register format
2.3. Dsize and Isize field format
2.4. Index/segment format for cache operations
2.5. Address format for ICache prefetch operations
3.1. ARM940T protection unit
3.2. Overlapping memory regions
4.1. 4KB cache used for the instruction and data caches
4.2. ARM940T Instruction/data cache addressing
4.3. Write buffer allocation
5.1. ARM940T clocking
5.2. Synchronous mode FCLK to BCLK zero phase delay
5.3. Synchronous mode FCLK to BCLK one phase delay
5.4. Asynchronous mode FCLK to BCLK zero cycle delay
5.5. Asynchronous mode FCLK to BCLK one cycle delay
6.1. Example LDR from address 0x108
6.2. Example LDM of 5 words from 0x108
6.3. LDM operation crossing a 4KB boundary
6.4. Example nonbuffered STR
6.5. Example STM
6.6. STM operation crossing a 4KB boundary
6.7. Example linefill from 0x100
6.8. Cache linefill and write back
6.9. Example 4-word data eviction
6.10. Example swap operation
6.11. Simultaneous cache misses
7.1. ARM940T coprocessor clocking
7.2. ARM940T LDC/STC cycle timing
7.3. ARM940T MCR/MRC transfer timing
7.4. ARM940T interlocked MCR
7.5. ARM940T late-cancelled CDP
7.6. ARM940T privileged instructions
7.7. ARM940T busy-waiting and interrupts
8.1. Typical debug system
8.2. Breakpoint timing
8.3. Watchpoint entry with data processing instruction
8.4. Watchpoint entry with branch
8.5. Test access port (TAP) controller state transitions
8.6. Clock switching on entry to debug state
8.7. Debug exit sequence
8.8. Debug state entry
8.9. ARM940T EmbeddedICE unit
8.10. Watchpoint control register for data comparison
8.11. Watchpoint control register for instruction comparison
8.12. Debug control register
8.13. Debug status register
8.14. Vector catch register
8.15. Debug comms control register
9.1. Using TrackingICE
10.1. AMBA test methodology
10.2. ARM940T integrated test harness
11.1. Single load interlock timing
11.2. Two cycle load interlock
11.3. LDM interlock
11.4. LDM dependent interlock
12.1. FCLK
12.2. BCLK
12.3. ARM940T FCLK timed coprocessor interface
12.4. ARM940T BCLK timed coprocessor interface
12.5. ARM940T FCLK related signal timing
12.6. ARM940T BCLK related signal timing
12.7. ARM940T SDOUTBS to TDO relationship
12.8. ARM940T nTRST to RSTCLKBS relationship
12.9. ARM940T JTAG output signal
12.10. ARM940T JTAG input signal timing
12.11. FCLK debug timing
12.12. BCLK debug timing
12.13. ARM940T FCLK related debug output timings
12.14. ARM940T BCLK related debug output timings
12.15. AHB signal timings
12.16. ARM940T TCK related debug output timings
12.17. nTRST to DBGRQI relationship
12.18. ARM940T EDBGRQ to DBGRQI relationship
12.19. ARM940T DBGEN to output relationship

List of Tables

2.1. ARM9TDMI implementation option
2.2. CP15 register map
2.3. CP15 abbreviations
2.4. ID code register
2.5. Cache type register format
2.6. Cache size encoding (M=0)
2.7. Cache associativity encoding (M=0)
2.8. Line length encoding
2.9. CP15 register 1
2.10. Clocking modes
2.11. Cachable register format 
2.12. Write buffer control register 
2.13. Protection space register format
2.14. Permission encoding
2.15. CP15 data protection region registers
2.16. CP15 instruction protection region registers
2.17. CP15 protection region register format 
2.18. Area size encoding
2.19. Cache operations writing to register 7
2.20. Lockdown register format
2.21. CP15 register 15
3.1. Protection register format
3.2. Region size encoding  
4.1. CP15 register 7 
4.2. Data write modes
5.1. Clock selection for external memory accesses
6.1. AMBA ASB transfer types
6.2. Burst transfers
6.3. Noncached LDR and fetch
7.1. Coprocessor availability
7.2. Handshake encoding
8.1. Public instructions
8.2. ID code register
8.3. Scan chain number allocation
8.4. Scan chain 4 addressing mode bit order
8.5. Scan chain 4 addressing mode bit order
8.6. Scan chain 4 reading mode bit order
8.7. Scan chain 5 addressing mode bit order
8.8. Scan chain 5 reading mode bit order
8.9. Scan chain 4 addressing mode bit order
8.10. ARM940T EmbeddedICE unit register map
8.11. Watchpoint control register for data comparison
8.12. Watchpoint control register for instruction comparison
8.13. Scan chain 15 format
8.14. Scan access mapping to CP15 register
8.15. Flush I-Cache
8.16. Scan chain 4 and 5 addressing mode 
8.17. Scan chains 4 and 5 reading mode 
9.1. ARM940T in TrackingICE 
10.1. Scan chain 0 bit order
11.1. Symbols used in tables
11.2. Instruction cycle bus times
11.3. Data bus instruction times
12.1. ARM940T timing parameters
A.1. AMBA signals
A.2. Coprocessor interface signals
A.3. JTAG and TAP controller signals
A.4. Debug signals
A.5. Miscellaneous signals

Proprietary Notice

Words and logos marked with ® or ™ are registered trademarks or trademarks owned by ARM Limited, except as otherwise stated below in this proprietary notice. Other brands and names mentioned herein may be the trademarks of their respective owners.

Neither the whole nor any part of the information contained in, or the product described in, this document may be adapted or reproduced in any material form except with the prior written permission of the copyright holder.

The product described in this document is subject to continuous developments and improvements. All particulars of the product and its use contained in this document are given by ARM in good faith. However, all warranties implied or expressed, including but not limited to implied warranties of merchantability, or fitness for purpose, are excluded.

This document is intended only to assist the reader in the use of the product. ARM Limited shall not be liable for any loss or damage arising from the use of any information in this document, or any error or omission in such information, or any incorrect use of the product.

Figure 8.5 reprinted with permission IEEE Std 1149.1-1990, IEEE Standard Test Access Port and Boundary-Scan Architecture Copyright 2000, by IEEE. The IEEE disclaims any responsibility or liability resulting from the placement and use in the described manner.

Confidentiality Status

This document is Non-Confidential. The right to use, copy and disclose this document may be subject to license restrictions in accordance with the terms of the agreement entered into by ARM and the party that ARM delivered this document to.

Product Status

The information in this document is final, that is for a developed product.

Revision History
Revision A12th February 1999First release.
Revision B22nd November 2000Second release.
Copyright © 1999, 2000 ARM Limited. All rights reserved.. All rights reserved.ARM DDI 0144B