2.1. ARM PrimeCell Smart Card Interface (PL130) overview

The PrimeCell Smart Card Interface (SCI) conforms to Part 1 of the Integrated Circuit Specification for Payment Systems Electromechanical Characteristics, Logical Interface, and Transmission Protocols (Version 3.0 June 1996). This standard is published jointly by Europay International S.A., Mastercard International Incorporated, and Visa International Service Association and is subsequently referred to as the EMV Standard. This standard refers to, and is based upon, the ISO 7816 series of standards. The user is expected to be familiar with both the EMV Standard and ISO 7816-3.

The PrimeCell SCI performs:

The host CPU reads and writes data and control information via the AMBA APB interface. The transmit and receive paths are buffered with internal FIFO memories allowing up to 8-bytes to be stored independently in both transmit and receive modes.

The PrimeCell SCI includes a programmable baud rate generator and, in conjunction with a secondary value counter, provides programmable elementary time units (etus).

This peripheral has been designed such that it allows close monitoring of all stages of a typical card session via mask enabled interrupts. The interrupt architecture allows a choice of:

The transmit and receive FIFO interrupts are asserted and de-asserted automatically depending on their programmed trigger threshold levels.

Parity errors are automatically checked by hardware on received data.

Interpretation of the received data stream is always performed by the user’s application software.

Card deactivation is initiated automatically via hardware on card removal, but it is also possible to deactivate the card via software by writing to the respective control register. Also a second deactivation request input is available for direct control via an alternative hardware source.

Although some parameter values are currently fixed by the EMV Specification, the design has taken into account that these may be changed in the future. The design strategy means that the user should be able to incorporate future changes to the specification with minimal effort.

A brief summary of the individual blocks of the design is given in the following sections.

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