A.2. On-chip signals

Table A.2 shows the non-AMBA on-chip signals from the block.

Table A.2. On-chip signals

NameType

Source/

destination

Description
SCIREFCLKInputClock generatorPrimeCell SCI reference clock
nSCIRSTInputReset controllerPrimeCell SCI reset signal to SCIREFCLK clock domain, active LOW. The reset controller must use BnRES to assert nSCIRST asynchronously but negate it synchronously with SCIREFCLK.
SCICARDININTROutputInterrupt controllerPrimeCell SCI card in interrupt (active HIGH).
SCICARDOUTINTROutputInterrupt controllerPrimeCell SCI card out interrupt (active HIGH).
SCICARDUPINTROutputInterrupt controllerPrimeCell SCI card powered up interrupt (active HIGH).
SCICARDDNINTROutputInterrupt controllerPrimeCell SCI card powered down interrupt (active HIGH).
SCITXERRINTROutputInterrupt controllerPrimeCell SCI character transmission error interrupt (active HIGH).
SCIATRSTOUTINTROutputInterrupt controllerPrimeCell SCI ATR start timeout interrupt (active HIGH).
SCIATRSDOUTINTROutputInterrupt controllerPrimeCell SCI ATR duration timeout interrupt (active HIGH).
SCIBLKTOUTINTROutputInterrupt controllerPrimeCell SCI block timeout interrupt between blocks (active HIGH).
SCICHTOUTINTROutputInterrupt controllerPrimeCell SCI character timeout interrupt between characters (active HIGH).
SCIRTOUTINTROutputInterrupt controllerPrimeCell SCI receive FIFO read timeout interrupt (active HIGH)
SCIRXTIDEINTROutputInterrupt controllerPrimeCell SCI receive FIFO tide mark reached interrupt (active HIGH).
SCITXTIDEINTROutputInterrupt controllerPrimeCell SCI transmit FIFO tide mark reached interrupt (active HIGH).
SCIINTROutputInterrupt controllerPrimeCell SCI interrupt (active HIGH). A single combined interrupt generated as an OR function of the twelve individually maskable interrupts above.
SCANMODEInputTest controllerPrimeCell SCI scan test hold input. This signal must be asserted HIGH during scan testing to ensure that internal data storage elements can be asynchronously reset.SCANMODE must be negated LOW during normal use or when applying manufacturing test vectors via the Test Interface Controller (TIC).

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