3.2. Summary of PrimeCell SCI registers

The PrimeCell SCI registers are shown in Table 3.1.

Table 3.1. PrimeCell SCI register summary

Address

Type

Width

Reset

value

Name

Description

SCI Base + 0x00

Read

Write

9

0x--

SCIDATA

SCIDATA

Data register.

SCI Base + 0x04

Read

Write

6

0x00

SCICR0

SCICR0

Control register 0.

SCI Base + 0x08

Read

Write

6

0x00

SCICR1

SCICR1

Control register 1.

SCI Base + 0x0c

Write

3

0x0

SCICR2

Control register 2.

SCI Base + 0x10

Read

Write

12

0x000

SCIIER

SCIIER

Interrupt enable register.

SCI Base + 0x14

Read

Write

6

0x00

SCIRETRY

SCIRETRY

Retry limit register.

SCI Base + 0x18

Read

Write

8

0x00

SCITIDE

SCITIDE

FIFO tide mark register.

SCI Base + 0x1c

Read

Write

5/0

0x00

SCITXCOUNT

SCITXCOUNTCLR

Transmit FIFO count register.

Transmit FIFO count clear register.

SCI Base + 0x20

Read

Write

5/0

0x00

SCIRXCOUNT

SCIRXCOUNTCLR

Receive FIFO count register.

Receive FIFO count clear register.

SCI Base + 0x24

Read

4

0xa

SCIFR

Flag register.

SCI Base + 0x28

Read

Write

16

0x0000

SCIRXTIME

SCIRXTIME

Receive read time-out register.

SCI Base + 0x2c

Read

Write

11

0x000

SCIISTAT

SCIISTAT

Smart Card status register.

SCI Base + 0x30

Read

Write

16

0x0000

SCISTABLE

SCISTABLE

De-bounce timer.

SCI Base + 0x34

Read

Write

16

0x0000

SCIATIME

SCIATIME

Activation event time.

SCI Base + 0x38

Read

Write

16

0x0000

SCIDTIME

SCIDTIME

Deactivation event time.

SCI Base + 0x3c

Read

Write

16

0x0000

SCIATRSTIME

SCIATRSTIME

Time to start of ATR reception.

SCI Base + 0x40

Read

Write

16

0x0000

SCIATRDTIME

SCIATRDTIME

Maximum duration of the ATD character stream.

SCI Base + 0x44

Read

Write

16

0x0000

SCIBLKTIME

SCIBLKTIME

Receive time-out between blocks.

SCI Base + 0x48

Read

Write

16

0x0000

SCICHTIME

SCICHTIME

Character to character time-out.

SCI Base + 0x4c

Read

Write

8

0x00

SCICLKICC

SCICLKICC

External Smart Card clock frequency.

SCI Base + 0x50

Read

Write

16

0x0000

SCIBAUD

SCIBAUD

Baud rate clock.

SCI Base + 0x54

Read

Write

8

0x00

SCIVALUE

SCIVALUE

SCIBAUD cycles.

SCI Base + 0x58

Read

Write

8

0x00

SCICHGUARD

SCICHGUARD

Character to character extra guard time.

SCI Base + 0x5c

Read

Write

8

0x00

SCIBLKGUARD

SCIBLKGUARD

Block guard time.

SCI Base + 0x60

Read

Write

2

0x0

SCISYNCCR

SCISYNCCR

Asynchronous/synchronous multiplexing control.

SCI Base + 0x64

Read

Write

2

0x0

SCISYNCDATA

SCISYNCDATA

Synchronous Smart Card data.

SCI Base + 0x68

Read

2

0x0

SCIRAWSTAT

Raw input/output and clock status.

SCI Base + 0x6c

Read

Write

12

0x00a

SCIIIR

SCIICR

Interrupt identification register/interrupt clear register.

SCI Base + 0x70

to 0x7c

-

-

-

-

Reserved.

SCI Base + 0x80

to 0xff

-

-

-

-

Reserved for test purposes.

Copyright © 1999 ARM Limited. All rights reserved.ARM DDI 0148B
Non-Confidential