4.3. Test registers

The PrimeCell SCI test registers are memory-mapped as follows shown in Table 4.1.

Table 4.1. Test registers memory map

AddressTypeWidth

Reset

Value

NameDescription

SCI Base + 0x80

Read/write

5

0x00

SCITCR

Test control register.

SCI Base + 0x84

Read/write

6

0x00

SCITMR

Test mode register.

SCI Base + 0x88

Read/write

4

0x0

SCITISR

Test input stimulus register.

SCI Base + 0x8c

Read

2

0x0

SCITOCR

Test output capture register.

SCI Base + 0x90

Read

16

0x0000

SCIDATATIME

Data timer read back register.

SCI Base + 0x94

Read

16

0x0000

SCIBAUDCNT

Baud counter read back register.

SCI Base + 0x98

Read

16

0x0000

SCIVALUECNT

Value counter read back register.

SCI Base + 0x9c

Read

16

0x0000

SCIRTSTBPRECNT

Receive read timeout counter/stable counter prescaler read back.

SCI Base + 0xa0

Read

16

0x0000

SCIACTTIME

Activation timer read back.

SCI Base + 0xa4

Read

16

0x0000

SCICLKICCCNT

Smart clock generating counter read back.

SCI Base + 0xa8

Read

4

0x0

SCISTATE

Control state machine status.

SCI Base + 0xac

to 0xbc

--

Reserved (for test purposes).

SCI Base + 0xc0

to 0xfc

Read/write

0

0x0

SCITCER

Test clock enable register.

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