4.3.1. SCITCR [16] (+0x80)

SCITCR is the test control register and specifies the clocking scheme to be used in test mode. It does this by controlling the clocking mode and the input pin multiplexing during test mode.

In the clock enable test mode, all clock inputs to the PrimeCell SCI are driven by the same signal. Test mode is said to have been entered when the TESTEN bit is set to 1. In test mode, if the TESTCLKEN bit is set to 1, test clocking is enabled. When test clocking is enabled, if the REGCLK bit is 0, a pulse is generated on the TESTCLKEN signal on every access to the SCI. When test clocking is enabled, if the REGCLK bit is 1, a pulse is generated on the TESTCLKEN signal only when the Test Clock Enable register (SCITCER) is accessed.

The TESTRST bit in the register allows the flip-flops in the design to be asynchronously reset in test mode. This helps to avoid cross propagation in simulations and resets the internal registers during production level testing.

The TESTINSPEL bit selects the source for the internal input signal for external non-AMBA inputs. Table 4.2 shows bit assignments for SCITCR.

Table 4.2. SCITCR register read/write bits

BitNameTypeDescription
15:5  Reserved, read unpredictable, should be written as 0.All bits are cleared to 0 on reset by BnRES.
4TESTINPSEL

Read/write

Test Input Select. By default, this bit is cleared to 0 for normal operation. This bit selects the source for the primary inputs.

When this bit is cleared to 0, the primary inputs are taken from the external pads (normal operation).When this bit is set to 1, the value programmed in SCITISR is used to determine the data bit used to drive the receive data path for external non-AMBA inputs while in test mode.

3TESTRST

Read/write

Test Reset. By default, this bit is cleared to 0 for normal operation when reset by BnRES.

When this bit is set to 1, a reset is asserted throughout the module, EXCEPT for the test registers (this simulates reset by BnRES being asserted to 0).

2REGCLKRead/write

Registered Clock Mode. This bit selects the internal test clock mode:

0 = Strobe clock mode is selected which generates a test clock enable on every APB access (read or write) to the block. Use of strobe clock mode allows testing with less test vectors when testing functions such as counters. The Test Clock Enable is generated from PENABLE ANDed with PSEL.

1 = Registered clock mode is selected which only generates a test clock enable on an APB access to the SCITCER location.This bit has no effect unless bit 0 and bit 1 are both set to 1.

This bit is cleared to 0 by default on reset by BnRES.

1TESTCLKENRead/write

Test Clock Enable. This bit selects the source of the test clock:

0 = The internal clock enable is forced continuously HIGH.

1 = The internal test clock enable is selected, so that test clocks are enabled for only one period of the input clock per APB access. The internal clock enable mode depends on the setting of bit 2.

This bit has no effect unless bit 0 is set to 1.

This bit is cleared to 0 by default on reset by BnRES.

0TESTENRead/write

Test Mode Enable. 0 = Normal operating mode is selected.

1 = Test mode is selected.

Bits 1 and 2 have no effect unless bit 0 is set to 1.

This bit is cleared to 0 by default on reset by BnRES.

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