2.3.2. Clock signals

The PrimeCell SCI has two input clock signals, PCLK and SCIREFCLK.

The SCIREFCLK frequency value should be selected in accordance with the chosen method of operation. For further details refer to

It is allowable to drive SCIREFCLK using the PCLK signal when the frequency value is suitable for the chosen method of operation, but separate clock signals may be required due to other system constraints.

However, there is a recommended constraint on the ratio of frequencies for PCLK and SCIREFCLK.


The frequency of SCIREFCLK must be less than twice the frequency of PCLK. If SCIREFCLK is more than twice the frequency of PCLK then transmission rates may not be fast enough to comply with the specification.

There is no restraint if the frequency of SCIREFCLK is less than the frequency of PCLK.

Copyright © 1999 ARM Limited. All rights reserved.ARM DDI 0148B