2.3.10. Transmit

Characters that are to be sent to the card are first written into the SCIDATA FIFO and then automatically transmitted to the card at timed intervals. Direction of communication is controlled by the MODE bit of the SCICR1 register. Changing from transmit to receive does not take place until the last character stored in the transmit FIFO has been sent. This enables the MODE bit to be written immediately after writing the last character in a block. This is necessary because the card can respond to the transmission almost immediately (minimum turnaround time measured from start bit to start bit is 16 etus for T0 and 22 etus for T1).

If character‑transmit handshaking is enabled (mandatory for T0), the input/output line is sampled at 1 etu after the parity bit. If the card indicates that it did not receive the character correctly, the character is retransmitted a maximum of TXRETRY times (set using the SCIRETRY register) before the transmission is aborted and a SCITXERRINTR interrupt generated. The interface waits for four etus after an error is detected before the character is retransmitted. If a character fails to be transmitted and a SCITXERRINTR interrupt is generated, the transmit/receive interlock mechanism must be reset by flushing the transmit FIFO before any subsequent transmit or receive operation.

The interval between successive characters sent by the interface is governed by the SCICHGUARD register, which defines the character guard time. SCICHGUARD is only used to control the transmission of characters and is not used by the receive hardware.

The minimum interval between the last character sent by the card and the next character sent by the interface is governed by the SCIBLKGUARD register, which defines the block guard time.

When the number of characters held in the transmit FIFO falls below the level defined in the SCITXTIDE register, a SCITXTIDEINTR interrupt is generated. The number of characters held in the transmit FIFO can be determined by reading the SCITXCOUNT register. Writing to the SCITXCOUNT register flushes the transmit FIFO.

Copyright © 1999 ARM Limited. All rights reserved.ARM DDI 0148B