2.3.4. Warm reset sequence

This section describes an ideal card session However, if the ATR sequence is found to be in error, as described in Response to an ideal card session, then the PrimeCell SCI will initiate a warm reset sequence in an attempt to restart reception of the ATR stream:

  1. Assert nSCICARDRST LOW.

  2. Maintain VCC and clock stable

  3. Put the PrimeCell SCI into reception mode

  4. Wait for SCIATIME Smart Card clock cycles

  5. De-assert nSCICARDRST HIGH.

The host initiates the activation sequence by writing a 1 to bit 0 (STARTUP) of the SCICR2 control register.

The ATR on the input/output line from the Smart Card will begin between 400 and 40000 cycles from reset de-assertion.

If the start bit of the ATR stream is not received within this time, then the PrimeCell SCI will automatically initiate the deactivation sequence without the need for software intervention.

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