2.3.5. Response to a non-ideal card session

The PrimeCell SCI has to resolve non-ideal transactions such as:

The PrimeCell SCI monitors each transaction stage via interrupt and status generation, allowing software to respond accordingly. For more detailed information on the individual and final shared interrupts, refer to Chapter 3 Programmer’s Model.

Notification of errors is provided to the host by the PrimeCell SCI via a choice of either twelve direct interrupts or their single ORed version, the SCI Interrupt Signal SCIINTR, coupled with subsequent reading of the SCI Interrupt Identification Register SCIIIR.

Note

In the following descriptions, setting of any of the twelve individual inputs implies that the SCIINTR signal is also consequently set.

Card removed at any time between activation and deactivation

The PrimeCell SCI must ensure that no electrical damage is caused to the card if it is removed whilst still powered up, that is, it must immediately be deactivated in a defined sequence.

Card deactivation takes precedence over any other operation and can be initiated by software or hardware. The card must be powered down in less than 1 millisecond. See Contact deactivation sequence and card removal on page 2‑14 for details of this sequence.

On recognition of the card being removed, that is, SCIDETECT transitioning from HIGH to LOW, the PrimeCell SCI asserts the SCI Card Out Interrupt SCICARDOUTINTR and sets bit [1], the SCI Card Out Interrupt Status bit (SCICARDOUTIS) of the SCIIIR register.

Card inserted, debounce time not met, then card removed

This is very similar to the above, though not as critical, as power will not been applied to the card. The card is only activated on successful completion of the debounce period. As above the card must immediately be deactivated using the controlled deactivation sequence.

On recognition of the card being removed, that is SCIDETECT transitioning from HIGH to LOW, the PrimeCell SCI asserts the SCI Card Out Interrupt SCICARDOUTINTR and sets bit [1], the SCI Card Out Interrupt Status bit (SCICARDOUTIS) of the SCIIIR register.

Card inserted, debounce time not met, no ATR start bit received within the specified time

The SCIATRSTIME register value is programmed with the value 40000. This represents the maximum number of Smart Card clock cycles after de-assertion of the SCICARDRST signal during which the start bit of the card’s ATR sequence should be received.

If the ATR start bit is not received before this maximum number of Smart Card clock cycles has expired, then the PrimeCell SCI asserts the ATR Start Timeout Interrupt SCIARTSTOUTINTR and sets bit 5 of the SCIIIR register, the SCI Card Out Interrupt Status bit (SCIATRSTOTIS).

The PrimeCell SCI will automatically initiate the deactivation sequence without the need for software intervention.

ATR start bit received, but time between two successive characters exceeds the specified time.

If the ATR start bit is received within the specified time, then the time between leading edges of the ATR characters is checked to be less than the specified maximum limit.

This value is programmed into the SCI Character Time register (SCICHTIME).

During the ATR, the delay between the leading edges of any two consecutive characters from the card shall be a minimum of 12, but not more than 9600 etus. See Table 2‑1 on page 2‑10 for more details of the definition of the initial etu values for ATR reception.

If the SCICHTIME value is exceeded at any time during reception of the ATR data stream, then the SCI Character TimeOut Interrupt signal (SCICHTOUTINTR) is asserted and bit 8, the SCI Character TimeOut Interrupt status bit (SCICHTOUTIS), of the SCIIIR register is set.

The host software will respond to the interrupt and initiate a warm reset sequence by writing a 1 to the WRESET bit of the SCICR2 control register.

ATR start received, but the duration of the total ATR data stream exceeded the specified time

The card shall transmit all the characters to be returned during an ATR within 19200 etus. This time is measured between the leading edge of the start bit of the first character (TS) and 12 etus after the leading edge of the start bit of the last character.

The maximum value, which is currently fixed at 19200 by the EMV Specification, is programmed into the SCI ATR Duration Time register (SCIATRDTIME). If the SCIATRDTIME time is not met, then the SCI ATR Duration TimeOut Interrupt signal SCIATRDTOUTINTR is asserted and bit 6, the SCI ATR TimeOut Status bit (SCIATRDTOUTIS) of the SCIIIR register is set.

The host software will respond to the interrupt and initiate a warm reset sequence by writing a 1 to the WRESET bit of the SCICR2 control register.

ATR received, but parity errors are found within the received data

If, during the reception of the ATR stream, an error such as parity failure is recognized by the PrimeCell SCI or the associated software, then the PrimeCell SCI will initiate a warm reset by writing a 1 to the WRESET bit of the SCICR2 control register.

Data transaction in progress, time for block arrival exceeded

If the maximum delay from start leading edges of the last character from the PrimeCell SCI, that gave the right to send to the card, and the first character sent by the card exceeds a specified time, then the PrimeCell SCI will assert the SCI Block TimeOut Interrupt (SCIBLKTOUTINTR) and set bit 7, the SCI Block TimeOut Interrupt Status (SCIBLKTOUTIS) bit, of the SCIIIR register.

The block timeout value is programmed by writing to the SCIBLKTIME register.

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