2.3.3. Response to an ideal card session

This section gives a brief overview of an ideal transaction sequence, and how it is monitored. Following this is a section that describes the typical errors that may occur during a non-ideal transaction and the ensuing actions.

Notification of errors is provided to the host by the PrimeCell SCI via a choice of:


In the following descriptions, setting of any of the 12 individual inputs implies that the SCIINTR signal is also consequently set.

Stages of a card session

A card session comprises the following stages:

PrimeCell SCI reset and initial configuration

The PrimeCell SCI is reset by the asynchronous LOW application of BnRES and nSCIRST. These signals are then synchronously removed with reference to their respective clocks. The PrimeCell SCI is then configured by writing the initial values listed in Table 2.1 in preparation for a card being inserted into a Smart Card Reader and subsequent communication.


The SCIDTIME register controls the timing of the card deactivation sequence and must be initialized before the activation sequence takes place. This is mandatory. Failure to carry out this action may result in damage to the card if it is removed prematurely.

Table 2.1. Initial configuration values

SCICR00x0The control register 0 is set to direct convention, even parity, receive/transmit handshaking disabled.
SCICR10x0Receive mode, timeouts initially disabled.
SCIIER0xfffEnable all interrupts.
SCISTABLE0x64For a 48MHz (21ns) reference clock, the stable (debounce) time is in terms of multiples of 1.38ms (0xffff x 21ns). An initial value of 136ms is proposed.
SCIATIME0xafc8The SCIATIME register must be programmed to between 40000 and 45000 (0xafc8) smart card clock cycles to satisfy the minimum cold and warm reset nSCICARDRST LOW time requirements.
SCIDTIME0x2710The SCIDTIME is in terms of reference clock periods. It times the three stages of the deactivation sequence. The total time of the deactivation sequence must not take longer than 1ms to complete. An initial value of 10000 (0x2710) periods is suggested which is equivalent to an SCIDTIME of approximately 0.21ms for a 48MHz (21ns) reference clock. This gives a total deactivation time of approximately 0.65ms.
SCIATRSTIME0x9c40The SCIATRSTIME is in terms of smart card clock cycles. After de-assertion of the reset nSCICARDRST signal, the start of the ATR sequence must occur within 40000 (0x9c40) smart card cycles.
SCIATRDTIME0x4b00The SCIATRDTIME is in terms of elementary time units (etus). The complete ATR character sequence must be received within 19200 (0x4b00) etus.
SCICHTIME0x2580The SCICHTIME is in terms of etus and is the maximum interval between the leading edges of two consecutive characters. In the case of the ATR sequence this is 9600 (0x2580) etus. It is also applicable to characters in the transaction data stream and is T = 0, or T = 1 mode dependent.
SCIRXTIDE0x0This is the receive FIFO tide level. Although a value of zero is proposed, any value between 0x0 and 0x7 can be used. With a value of zero, the SCIRXTIDEINTR interrupt is generated when the initial TS character is loaded into the receive FIFO.
SCICLKICC0x17The SCICLKICC value is used to divide down the reference clock to provide the smart card clock. The final smart card frequency should be within the range 1-5MHz. For a 48MHz reference clock, SCICLKICC should be programmed with a value of 23 (0x17) to provide an initial 1MHz Smart Card clock frequency.
SCIBAUD0x174For a 48MHz reference clock, 1MHz smart card clock, and an SCI value of 10 (0xA), then SCIBAUD should be programmed to 178A (0x6f8)
SCIVALUE0x10An SCIVALUE value of 10 (0xa) is proposed as the sample value.

Smart card insertion and detection

A Smart Card is inserted into the Smart Card Reader.

The Smart Card Reader signals to the PrimeCell SCI that a card has been detected by setting the SCIDETECT signal high. In response to this, the PrimeCell SCI starts its debounce timer.

The Smart Card must remain in the interface for the debounce period, which is initially defined by the value written to the SCISTABLE register.

On expiry of the debounce period, the PrimeCell SCI notifies the host that a card has been successfully inserted by asserting the SCI Card In Interrupt signal SCICARDININTR and setting bit [0], the SCICARDINIS bit, of the SCIIIR status register.

At this point there are no clocks or power applied to the Smart Card and the input/output signals are held LOW by the interface. These signals are then applied in a controlled manner by the activation sequence.

Contact activation and cold reset sequence

The host now signals the PrimeCell SCI that it can activate the card, that is power up the inserted card in an ordered manner. The PrimeCell SCI activation sequence has been divided into three equal phases, timed by the value programmed in the SCI activation time register SCIATIME.

The PrimeCell SCI activation sequence includes the cold reset sequence which must be in effect for between 40000 and 45000 Smart Card clock cycles. This is programmed using the SCIATIME register.

The PrimeCell SCI performs the following activation sequence:

  1. Assert nSCICARDRST low.

  2. Wait for SCIATIME Smart Card clock cycles.

  3. Enable VCC, configure SMDATA signal as high impedance.

  4. Wait for SCIATIME Smart Card clock cycles.

  5. Enable SCICLKOUT clock.

  6. Wait for SCIATIME Smart Card clock cycles.

  7. De-assert nSCICARDRST high.

The host initiates the activation sequence by writing a 1 to bit 0 (STARTUP) of the SCI control register 2 (SCICR2).

The PrimeCell SCI notifies the host that the activation sequence is complete by asserting the SCI card up interrupt signal SCICARDUPINTR and setting bit [2], SCICARDUPIS, within the SCIIIR.

The ATR on the input/output line from the Smart Card will begin between 400 and 40000 cycles from reset de-assertion.

Answer To Reset sequence

The ATR sequence contains information about the card requirements for subsequent data transactions. The first character within the ATR stream is called the TS character and contains the convention information (direct or inverse format) on how the remaining ATR and future data transaction characters will be interpreted.

On reception of the first character, the SCI RXTIDE interrupt SCIRXTIDEINTR signal is asserted and bit [10], the SCI RXTIDE interrupt status bit SCIRXTIDEIS is set within the SCIIIR status register.

The PrimeCell SCI should read this character, establish the respective required convention and then, if necessary, reprogram the SCI control register 0 (SCICR0). It is also recommended that the RXFIFO RXTIDE level be programmed to a higher value.

These processes should be completed prior to the start of reception of the next character.

In brief, the ATR sequence includes configuration values for:

  • the clock frequency

  • baud rate

  • guard times

  • protocol type.

The remainder of the ATR sequence is received, read via the RXFIFO in the selected convention, interpreted by the host software and the PrimeCell SCI programmed accordingly with the extracted values.

Execution of a transaction

After the interface has been configured by extracting the parameters from the ATR stream, host to card communication, and vice versa, can now proceed.

The direction of flow is controlled via the value written to bit [2], the MODE bit, in the SCI control register 1 (SCICR1).

The host is always in control of how many characters it sends to the card and how many characters it expects to be returned by the card.

The character streams must meet the timing requirements of either the T0 or T1 protocol. These are covered in TBD EMV character timing for T=0 (character protocol) on page 2‑21 and TBD EMV character timing for T=1 (block protocol) on page 2‑22.

Contact deactivation sequence and card removal

The final step in a typical card session is contact deactivation where the signals and power are removed in a defined sequence. Contact deactivation takes precedence over all other operations in order that the card is not electrically damaged.

The deactivation sequence can be initiated by software by writing a 1 to bit [1], the FINISH bit, of the SCICR2 register. Also, there are two hardware signals which can be used:

  • On detection of a cards removal at any time in a session, signified by the SMIDETECT signal being low, then contact deactivation will be initiated. The SMIDECTECT signal usually originates from a Smart Card reader.

  • In addition, it is possible to initiate contact deactivation by asserting the signal SCIDEREQ which may be fed from an alternative source other than a Smart Card reader.

The PrimeCell SCI deactivation sequence has been divided into three equal phases, timed by the value programmed in the SCI Deactivation Time (SCIDTIME) register and is in terms of reference clock SCIREFCLK periods.

The PrimeCell SCI deactivation sequence must complete within 1 millisecond. This means that the SCIDTIME register needs to be programmed with a third of the total time. For example, for an SCIREFCLK frequency of 48MHz (period 21ns) an SCIDTIME value of 10000 would equate to a total deactivation time of around 0.65ms.

The PrimeCell SCI performs the following deactivation sequence:

  1. Assert nSCICARDRST low.

  2. Wait for SCIATIME reference clock (SCIREFCLK) cycles.

  3. Drive SCICLKOUT low.

  4. Wait for SCIATIME reference clock (SCIREFCLK) cycles.

  5. Drive nSCIDATAEN high.

  6. Wait for SCIATIME reference clock (SCIREFCLK) cycles.

  7. Drive VCC low.

On completion of the deactivation sequence, the PrimeCell SCI asserts the SCI Card Down Interrupt signal SCICARDDNINTR and sets bit [3], the SCI Card Down Interrupt Status bit SCICARDDNIS, of the SCIIIR status register.

The card may then be safely removed if desired, but it may remain and be re-activated for another transaction if so required by the host.

On recognition of the card being removed, that is, SCIDETECT transitioning from HIGH to LOW, the PrimeCell SCI asserts the SCI Card Out Interrupt SCICARDOUTINTR and sets bit [1], the SCI Card Out Interrupt Status bit (SCICARDOUTIS) of the SCIIIR register.

Copyright © 1999 ARM Limited. All rights reserved.ARM DDI 0148B