2.3.1. Interface reset

The PrimeCell SCI is reset by the global reset signal BnRES and a block-specific reset signal nSCIRST. An external reset controller must use BnRES to assert nSCIRST asynchronously and negate it synchronously to SCIREFCLK. BnRES should be asserted LOW for a period long enough to reset the slowest block in the on-chip system, and then taken HIGH again. The PrimeCell SCI requires BnRES to be asserted for at least one period of PCLK and nSCIRST to be asserted for at least one period of SCIREFCLK.

The values of the registers after reset are detailed in Chapter 3 Programmer’s Model.

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