2.3.7. Character framing

Figure 2.6 shows the structure of a character. Each character consists of:

The guard time is the delay between the trailing edge of the parity bit of a character, and the leading edge of the start bit of the next character. The guard time for characters transmitted by the interface is controlled by the SCICHGUARD register.

Figure 2.6. Character structure

Figure 2.7 shows how the interface interprets characters transmitted from the card. At time TS, the card pulls the bidirectional input/output line LOW to begin the start bit.

Figure 2.7. Character timing

The interface detects the leading edge of the start bit after four reference clock cycles. The input/output line is sampled at RS, approximately half an etu after the leading edge of the start bit. If the input/output line is not LOW, the start bit is deemed to be invalid and is ignored by the interface.

The first data bit is sampled at 1 etu after RS, and subsequent data bits (including the parity bit) are sampled at 1 etu intervals. The T0 protocol defines a mechanism whereby the receiver can request retransmission of a character by pulling the input/output line LOW during the guard time following the character. When a retransmission is requested, the interface starts to pull the input/output line LOW at RAK.

The transmitter (the card in this case) samples the input/output line at TAK. The interface holds the input/output line for a total of 2 etus. This is shown in Figure 2.8.

Figure 2.8. To transmit request

Copyright © 1999 ARM Limited. All rights reserved.ARM DDI 0148B