2.2.3. Transmit and receive logic

This block implements the main functionality of the PrimeCell SCI with the control information being fed from the PrimeCell SCI control block. It contains all the counters used for timing the various stages of transactions during a card session. Also, it drives all the card control signals with the exception of data.

In this implementation some counters are multi-purpose, that is, they are loaded with values required by a particular transaction stage, thereby minimizing the logic required to perform the overall function.

The SCIBAUDCNT and SCIVALUECNT counters provide the means of performing the bit rate conversion and bit rate adjustment. Together they define the elementary time unit (etu) period.

The card clock, SCICLKOUT, is derived from the output of the SCICLKICCCNT divide counter.

The SCIACTTIME counter is multi-purpose and is used for six different operations:

The SCIDATATIME counter is a multi-purpose counter that is used to measure:

The SCIACTTIME and SCIDATATIME counters are controlled by the SCI Control block.

The transmit and receive block controls the sequencing of the power, clock, reset and data line during activation and deactivation processes.

With the exception of the transmit and receive FIFO interrupts, this block generates all the remaining interrupts that provide a means of monitoring the individual stages of a card session.

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