2.2.5. Transmit FIFO

The transmit FIFO is an 8-deep 8-bit wide circular buffer. Reads and writes to the transmit FIFO result in an access to buffer locations pointed to by a read and write pointer respectively. The transmit FIFO is used to buffer data that is subsequently sent to the card.

The Transmit Tide Mark Interrupt SCITXTIDEINTR is generated from within this block and is asserted when the level falls below the programmed value.

If there is an unsuccessful transmission when using the T0 protocol, the PrimeCell SCI asserts the SCI Transmit Error Interrupt (SCITXERRINTR) and sets bit [4], the SCI Transmit Error Interrupt Status (SCITXERRIS) bit, of the SCIIIR register. The PrimeCell SCI will stop transmitting and before any further characters can be transmitted, the error condition must be cleared by flushing the transmit FIFO.

Copyright © 1999 ARM Limited. All rights reserved.ARM DDI 0148B