2.2.6. Receive FIFO

The receive FIFO is an 8-deep 9-bit wide circular buffer. Reads and writes to the receive FIFO result in an access to buffer locations pointed to by a read and write pointer respectively. Data is stored in the least significant eight bits, and the ninth bit is set when a parity error is detected on the received data.

The SCIRXTIDEINTR interrupt is generated from within this block and is asserted when the level rises above the programmed value.

An SCI Receive Timeout Interrupt (SCIRTOUTINTR) is asserted and bit [9], the SCI Receive Timeout Status (SCIRTOUTIS), of the SCIIIR register is set under the following condition:

The receive FIFO contains at least one character, and no characters have been read for a time corresponding to the value programmed in the SCIRXTIME register.

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