4.3.8. SCIRTSTBPRECNT:[16](+0x9c)

SCIIRTSTBPRECNT is the receive read timeout counter/stable counter prescaler read back register. It returns the current state of the receive read timeout counter/stable counter prescaler. shows bit assignments for SCIRTSTBPRECNT.

Table 4.9. SCIRTSTBPRECNT register read bits

BitNameTypeDescription
[15:0]RTSTBRECNTReadStatus of receive read timeout counter/stable counter prescaler.
Copyright © 1999 ARM Limited. All rights reserved.ARM DDI 0148B
Non-Confidential