4.3.12. SCITCER[0](+0xc0 to 0xfc)

SCITCER is the test clock enable register and is a virtual register that is selected for address offsets from 0xc0 to 0xfc. In registered clock mode, a test clock enable is produced each time this register is accessed. Reads return zeros and write data is ignored. Table 4.13 shows bit assignments for SCITCER.

Table 4.13. SCITCER register read/write bits


When in registered clock mode (refer to SCITCR [16] (+0x80)), a test clock enable is produced only when this register is accessed (read or write).

A read will return zeros.

Write data is ignored.

SCITCER has a multiple word space in the register address map to allow for the generation of multiple test clock enable pulses.

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