3.3.5. SCIIER: [12] (+0x10)

SCIIER is the interrupt enable register and contains twelve bits that are used to enable the twelve interrupts. Table 3.6 shows bit assignments for SCIIER.

Note

The interrupt status bits visible in the SCIIIR register are free from masking. This is to allow polled mode of operation in systems which do not use an interrupt controller. Software can read the interrupt status bits through the SCIIIR even if their corresponding mask bits are set. Clearing the mask bits will not clear the interrupt status. However the pin-level interrupts will be cleared. The status bits are ANDed with the mask bits to create the pin-level interrupts.

Table 3.6. SCIIER register read/write bits

Bits

Name

Type

Function

11

SCITXTIDEIE

Read/write

Interrupt enable for SCITXTIDEINTR.

10

SCIRXTIDEIE

Read/write

Interrupt enable for SCIRXTIDEINTR.

9

SCIRTOUTIE

Read/write

Interrupt enable for SCIRTOUTINTR.

8

SCICHTOUTIE

Read/write

Interrupt enable for SCICHTOUTINTR.

7

SCIBLKTOUTIE

Read/write

Interrupt enable for SCIBLKTOUTINTR.

6

SCIATRDTOUTIE

Read/write

Interrupt enable for SCIATRDTOUTINTR.

5

SCIATRSTOUTIE

Read/write

Interrupt enable for SCIATRSTOUTINTR

4

SCITXERRIE

Read/write

Interrupt enable for SCITXERRINTR.

3

SCICARDDNIE

Read/write

Interrupt enable for SCICARDDNINTR.

2

SCICARDUPIE

Read/write

Interrupt enable for SCICARDUPINTR.

1

SCICARDOUTIE

Read/write

Interrupt enable for SCICARDOUTINTR.

0

SCICARDINIE

Read/write

Interrupt enable for SCICARDININTR.

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