3.3.25. SCISYNCCR: [2] (+0x60)

SCISYNCCR is the asynchronous/synchronous multiplexing register and is used to select the sources of the Smart Card clock and the input/output lines.

The Smart Card can operate in either asynchronous mode, where the clock is derived from the reference clock and data is driven directly by the interface or the card, or synchronous mode, where the system processor provides the clock and data by writing appropriate values to the SCISYNCDATA register. Table 3.28 shows bit assignments for SCISYNCCR.

Table 3.28. SCISYNCCR register read/write bits

Bits

Name

Type

Function

1

SELCLK

Read/write

Selects the source of the Smart Card clock.

0 = The Smart Card clock is derived from the reference clock.

1 = SCISYNCDATA register bit 1 (WCLK) drives the SCICLK Smart Card clock.

0

SELDATA

Read/write

Selects the signal used to drive the input/output line.

0 = FIFO data drives the SCIDATA input/output line.

1 = SCISYNCDATA register bit 0 (WDATA) drives the SCIDATA input/output line.

Copyright © 1999 ARM Limited. All rights reserved.ARM DDI 0148B
Non-Confidential