3.3.26. SCISYNCDATA: [4] (+0x64)

SCISYNCDATA is the synchronous Smart Card data register and contains the source of alternate values to be used to drive the Smart Card input/output and clock signal. Table 3.29 shows bit assignments for SCISYNCDATA.

Table 3.29. SCISYNCDATA register read/write bits

Bits

Name

Type

Function

3

WCLKEN

Read/write

If SELCLK = 0 and WCLKEN = 0, the SCICLKEN line is forced LOW.

2

WDATAEN

Read/write

If SELDATA = 0 and WDATAEN = 0, the SCIDATAEN line is forced LOW.

1

WCLK

Read/write

If SELCLK = 1, the Smart Card clock is driven with WCLK.

0

WDATA

Read/write

If SELDATA = 1 and WDATA = 0, the input/output line is forced LOW.

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