3.3.7. SCITIDE: [8] (+0x18)

SCITIDE is the FIFO tide mark register and is used to set the trigger points for the TXTIDE and RXTIDE interrupts.

The RXTIDE field of this register (7:4) contains a trigger point for the receive FIFO. When the number of characters in the receive FIFO exceeds RXTIDE, an RXTIDE interrupt is generated. Setting RXTIDE to 0 causes an interrupt as soon as the receive FIFO is non-empty. A value of 8 or more prevents any interrupt from occurring. An RXTIDE interrupt can only occur when the MODE bit of the SCICR1 register is set to 0 (receive).

The TXTIDE field of this register (3:0) contains the trigger point for the TXTIDE interrupt. When the number of characters in the transmit FIFO falls below this threshold, a TXTIDE interrupt is generated. Setting these bits to 0 prevents TXTIDE interrupts from being generated. Only values between 0 and 8 (inclusive) are valid.


Writes to the TXFIFO register are allowed only if the MODE bit is set for transmission. The TXTIDE interrupt, however, is not qualified with the MODE bit. This allows the software to be notified of the current fill level of the transmit FIFO even after the data direction has shifted from transmit to receive. However, the actual act of filling the transmit FIFO should be done based on higher level software considerations and not purely on the fact that the transmit FIFO has room for more data. By not qualifying the TXTIDE interrupt with the MODE bit, system performance may be increased since the interrupt is being raised as early as possible.

A TXTIDE interrupt can only occur if the MODE bit of the SCICR1 register is set to 1 (transmit).

A character is not removed from the transmit FIFO until it has been successfully transmitted. Table 3.8 shows bit assignments for SCITIDE.

Table 3.8. SCITIDE register read/write bits








Trigger point for SCIRXTIDEINTR.




Trigger point for SCITXTIDEINTR.

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