3.3.9. SCIRXCOUNT/SCIRXCOUNTCLR: [5/0] (+0x20)

SCIRXCOUNT/SCIRXCOUNTCLR is the receive FIFO count/receive FIFO count clear register. It returns the number of characters in the receive FIFO when read, and flushes the receive FIFO when written (with any value). Table 3.10 shows bit assignments for SCIRXCOUNT/SCIRXCOUNTCLR.

Table 3.10. SCIRXCOUNT/SCIRXCOUNTCLR register read/write bits

Bits

Name

Type

Function

4:0

RXCOUNT

Read

Receive FIFO count.

0

RXCOUNTCLR

Write

Receive FIFO count clear.

Copyright © 1999 ARM Limited. All rights reserved.ARM DDI 0148B
Non-Confidential