3.3.13. SCISTABLE: [16] (+0x30)

SCISTABLE is the debounce timer register and determines how long the SCIDETECT signal must hold a stable HIGH value, before the interface registers the insertion of a card. This is notified by setting the CARDININTR interrupt. Table 3.15 shows bit assignments for SCISTABLE.

Table 3.15. SCISTABLE register read/write bits








Stores the debounce time.

The debounce timer is constructed as a 16-bit counter feeding a programmable 8-bit counter, the former being loaded with 0xffff and the latter with the value contained in the SCISTABLE register. When enabled, the 16-bit counter decrements the 8-bit counter value until it reaches zero.

The logic is configured to provide a debounce time of (SCISTABLE + 1) multiples of the 16-bit full count.

For a 48MHz reference clock, this gives a programmable debounce time in the range 1.38ms to 350.28ms in 1.38ms steps.

The 16-bit counter can be bypassed for test purposes by setting the EXDBNCE bit HIGH. The reference clock then feeds the 8-bit SCISTABLE counter, with the interrupt status and signals being set when this counter reaches zero.

If the debounce period is satisfied, an SCICARDININTR interrupt is set.


After completion of the card deactivation sequence, the SCICARDININTR will be reset. A falling edge on SCIDETECT and a rising edge on SCIDEACREQ immediately resets SCICARDININTR.

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