3.3.16. SCIATRSTIME: [16] (+0x3c)

SCIATRSTIME is the time to start of ATR reception register. It defines the receive timeout threshold from the deassertion of SCICARDRST to the start of the first character in the ATR. This is specified in Smart Card clock cycles and its initial value is 40000 Smart card clock cycles.

The time in seconds, from the deassertion of SCICARDRST to the start of the first character in the ATR, will vary with Smart Card clock frequency.

On timeout, this timer will set an interrupt, SCIATRSTOUTINTR. Table 3.18 shows bit assignments for SCIATRSTIME.

Table 3.18. SCIATRSTIME register read/write bits

Bits

Name

Type

Function

15:0

ATRSTIME

Read/write

ATR reception start timeout threshold from the deassertion of nSCICARDRST.

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