3.3.18. SCIBLKTIME: [16] (+0x44)

SCIBLKTIME is the receive timeout between blocks register. It is used to configure the maximum delay from the leading edge of the last character that gave the right to send to the card, and the first character to be sent by the card. SCIBLKTIME applies to both T0 and T1 protocols:

Failure to meet the SCIBLKTIME value results in the setting of the internal SCIBLKTOUTINTR interrupt bit in the SCIIR register, and the external SCIBLKTOUTINTR interrupt signal. Table 3.20 shows bit assignments for SCIBLKTIME.

Note

The SCIBLKTIME parameter is not applicable to the ATR reception. the reception of the first character of the ATR stream must not exceed the value programmed in the SCIATRSTIME register, which is in terms of Smart Card clock cycles. The SCIATRSTIME value is defined as 40000 Smart Card clock cycles.

Table 3.20. SCIBLKTIME register read/write bits

Bits

Name

Type

Function

15:0

BLKTIME

Read/write

Defines the time for block timeout.

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