3.3.2. SCICR0: [6] (+ 0x04)

SCICR0 is control register 0. It configures the convention for interpreting characters, controls parity convention and enables the handshake mechanism to indicate that a parity error has occurred. The initial character returned by the card in the ATR sequence determines the convention.

There are two conventions:

Inverse

A LOW state on the input/output line is interpreted as logic one and the Most Significant Bit (MSB) of the data byte is the first bit after the start bit.

Direct

A LOW state on the input/output line is interpreted as logic zero and the Least Significant Bit (LSB) of the data byte is the first bit after the start bit.

Separate bits are used to control the logic sense and the bit ordering. This allows for nonstandard conventions to be configured.

The register bits (0 to 1) should be set to 00 before reading the initial (TS) character from the Answer To Reset (ATR) stream. The TS character determines the convention that the remainder of the ATR stream has been encoded with.

Inverse convention is configured by writing 11 to SCICR0[1:0] after reading the TS character and before reading any subsequent characters in the ATR.

The register bits 2 and 4 control the parity convention used (odd or even parity) and bits 3 and 5 are used to enable the handshaking mechanism. The handshaking mechanism is initiated by the receiver pulling down the input/output line whenever a parity error has occurred, and is ended by a character retry. Separate controls exist for the transmit and receive paths. The maximum number of attempts made to either transmit or receive a character is specified in the SCIRETRY register.

Character retry is not applied during ATR reception, hence this handshake should be programmed initially with the value 0x0.

Bits 2 to 5 should be set to 0xa if the T=0 protocol is requested by the contents of the initial (TS) character of the ATR stream. Table 3.3 shows bit assignments for SCICRO.

Table 3.3. SCICR0 register read/write bits

Bits

Name

Type

Function

5

RXNAK

Read/write

Enables character receipt handshaking.

If TXNAK = 0, the SCI pulls the input/output line LOW if it detects a parity error.

If TXNAK = 1, the SCI does not pull the input/output line LOW if it detects a parity error.

4

RXPARITY

Read/write

Receive parity setting.

0 = Even parity.

1 = Odd parity.

3

TXNAK

Read/write

Enables character transmission handshaking.

If TXNAK = 0, the SCI does not check to see if the receiver has pulled the input/output line LOW to indicate a parity error.

If TXNAK = 1, the SCI checks, after each character has been transmitted, to see if the receiver has pulled the input/output line LOW to indicate a parity error.

2

TXPARITY

Read/write

Transmit parity setting.

0 = Even parity.

1 = Odd parity.

1

ORDER

Read/write

Specifies ordering of the data bits.

0 = LOW interpreted as logic 0, lsb is the first bit after the start bit (direct convention).

1 = LOW interpreted as logic 1, msb is the first bit after the start bit (inverse convention).

0

SENSE

Read/write

Inverts sense of input/output line for data and parity bits.

0 = Direct convention.

1 = Inverse convention.

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