ARM PrimeCell ™ SmartCard Interface (PL130) Technical Reference Manual

Table of Contents

About this Technical Reference Manual
Intended audience
Using this Technical Reference Manual
Further reading
Feedback on this product
Feedback on this Technical Reference Manual
1. Introduction
1.1. About the ARM PrimeCell Smart CardInterface (PL130)
1.1.1. Features of the PrimeCell SCI
1.1.2. Programmable parameters
1.2. AMBA compatibility
2. Functional Overview
2.1. ARM PrimeCell Smart Card Interface(PL130) overview
2.2. PrimeCell SCI functional description
2.2.1. AMBA APB interface
2.2.2. Register block
2.2.3. Transmit and receive logic
2.2.4. SCI control logic
2.2.5. Transmit FIFO
2.2.6. Receive FIFO
2.2.7. Test registers and logic
2.3. PrimeCell SCI operation
2.3.1. Interface reset
2.3.2. Clock signals
2.3.3. Response to an ideal card session
2.3.4. Warm reset sequence
2.3.5. Response to a non-ideal card session
2.3.6. Data transfer
2.3.7. Character framing
2.3.8. EMV character timing for T=0 (characterprotocol)
2.3.9. EMV character timing for T=1 (block protocol)
2.3.10. Transmit
2.3.11. Receive
2.3.12. Block time and time between barriers
2.3.13. Parity error
2.3.14. RXREAD interrupt
3. Programmer’s Model
3.1. About the programmer’s model
3.2. Summary of PrimeCell SCI registers
3.3. Register descriptions
3.3.1. SCIDATA: [9]( + 0x00)
3.3.2. SCICR0: [6]( + 0x04)
3.3.3. SCICR1: [6] (+0x08)
3.3.4. SCICR2: [3] (+0x0c)
3.3.5. SCIIER: [12] (+0x10)
3.3.6. SCIRETRY: [6] (+0x14)
3.3.7. SCITIDE: [8] (+0x18)
3.3.8. SCITXCOUNT/SCITXCOUNTCLR: [5/0] (+0x1c)
3.3.9. SCIRXCOUNT/SCIRXCOUNTCLR: [5/0] (+0x20)
3.3.10. SCIFR: [4] (+0x24)
3.3.11. SCIRXTIME: [16] (+0x28)
3.3.12. SCIISTAT: [10] (+0x2c)
3.3.13. SCISTABLE: [16] (+0x30)
3.3.14. SCIATIME: [16] (+0x34)
3.3.15. SCIDTIME: [16] (+0x38)
3.3.16. SCIATRSTIME: [16] (+0x3c)
3.3.17. SCIATRDTIME: [16] (+0x40)
3.3.18. SCIBLKTIME: [16] (+0x44)
3.3.19. SCICHTIME: [16] (+0x48)
3.3.20. SCICLKICC: [8] (+0x4c)
3.3.21. SCIBAUD: [16] (+0x50)
3.3.22. SCIVALUE: [8] (+0x54)
3.3.23. SCICHGUARD: [8] (+0x58)
3.3.24. SCIBLKGUARD: [8] (+0x5c)
3.3.25. SCISYNCCR: [2] (+0x60)
3.3.26. SCISYNCDATA: [4] (+0x64)
3.3.27. SCIRAWSTAT: [2] (+0x68)
3.3.28. SCIIIR/SCIICR: [12] (+0x6c)
4. Programmer’s Model for Test
4.1. PrimeCell SCI test harness overview
4.2. Scan testing
4.3. Test registers
4.3.1. SCITCR [16] (+0x80)
4.3.2. SCITMR [6] (+0x84)
4.3.3. SCITISR:[4] (+0x88)
4.3.4. SCITOCR:[2](+0x8c)
4.3.5. SCIDATATIME: [16] (+0x90)
4.3.6. SCIBAUDCNT:[16](+0x94)
4.3.7. SCIVALUECNT:[16](+0x98)
4.3.8. SCIRTSTBPRECNT:[16](+0x9c)
4.3.9. SCIACTTIME:[16](+0xa0)
4.3.10. SCICLKICCCNT:[16](+0xa4)
4.3.11. SCISTATE:[4](+0xa8)
4.3.12. SCITCER[0](+0xc0 to 0xfc)
A. ARM PrimeCell Smart Card Interface (PL130) Signal Descriptions
A.1. AMBA APB signals
A.2. On-chip signals
A.3. Signals to pads

List of Tables

2.1. Initial configuration values
3.1. PrimeCell SCI register summary
3.2. SCIDATA register read/write bits
3.3. SCICR0 register read/write bits
3.4. SCICR1 register read/write bits
3.5. SCICR2 register write bits
3.6. SCIIER register read/write bits
3.7. SCIRETRY register read/write bits
3.8. SCITIDE register read/write bits
3.9. SCITXCOUNT/SCITXCOUNTCLR register read/write bits
3.10. SCIRXCOUNT/SCIRXCOUNTCLR register read/write bits
3.11. SCIFR register read bits
3.12. SCIRXTIME register read/write bits
3.13. RXTIME ranges and resolutions
3.14. SCIISTAT register read/write bits
3.15. SCISTABLE register read/write bits
3.16. SCIATIME register read/write bits
3.17. SCIDTIME register read/write bits
3.18. SCIATRSTIME register read/write bits
3.19. SCIATRSTIME register read/write bits
3.20. SCIBLKTIME register read/write bits
3.21. SCICHTIME register read/write bits
3.22. SCICLKICC register read/write bits
3.23. SCIBAUD register read/write bits
3.24. SCIVALUE register read/write bits
3.25. SCICHGUARD register read/write bits
3.26. SCIVALUE register read/write bits
3.27. SCIBLKGUARD register read/write bits
3.28. SCISYNCCR register read/write bits
3.29. SCISYNCDATA register read/write bits
3.30. SCIRAWSTAT register read bits
3.31. SCIIIR/SCIICR register read/write bits
4.1. Test registers memory map
4.2. SCITCR register read/write bits
4.3. SCITMR register read/write
4.4. SCITISR register read/writebits
4.5. SCITOCR register read bits
4.6. SCIDATATIME register read bits
4.7. SCIBAUDCNT register read bits
4.9. SCIRTSTBPRECNT register read bits
4.10. SCIACTTIME register read bits
4.11. SCICLKICCCNT register read bits
4.12. SCISTATE register read bits
4.13. SCITCER register read/write bits
A.1. AMBA APB signal descriptions
A.2. On-chip signals
A.3. Signals to pads

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This document is intended only to assist the reader in theuse of the product. ARM Limited shall not be liable for any lossor damage arising from the use of any information in this document,or any error or omission in such information, or any incorrect useof the product.


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Product Status

The information in this document is final, that is for a developedproduct.

Revision History
Revision A January1996 First release.
Revision B March1998 Second release.
Copyright © 1999 ARM Limited. All rights reserved. ARM DDI 0148B