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| Home > Caches, Write Buffer, and Physical Address TAG (PA TAG) RAM > Physical address TAG RAM |
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The ARM920T implements a Physical Address (PA) TAG RAM in order to perform write-backs from the DCache.
A write-back occurs when dirty data, that is about to be overwritten by linefill data, comes from a memory region that is marked as a write-back region. This data is written back to main memory to maintain memory coherency.
Dirty data is data that has been modified in the cache, but not updated in main memory.
When a line is written into the data cache, the PA TAG is written into the PA TAG RAM. If this line has to be written back to main memory, the PA TAG RAM is read and the physical address is used by the AMBA ASB interface to perform the write-back.
The PA TAG RAM array for a 16KB DCache comprises eight segments x 64 rows per segment x 26 bits per row. There are two test interfaces to the PA TAG RAM:
debug interface, see Scan chain 4 - debug access to the PA TAG RAM
AMBA test interface, see PA TAG RAM test.
| Copyright © 2000, 2001 ARM Limited. All rights reserved. | ARM DDI 0151C |
| Non-Confidential | |
| PDF version | |
| Home > Caches, Write Buffer, and Physical Address TAG (PA TAG) RAM > Physical address TAG RAM |