4.3. DCache and write buffer

The ARM920T processor includes a 16KB DCache and a write buffer to reduce the effect of main memory bandwidth and latency on data access performance. The DCache has 512 lines of 32 bytes (8-words), arranged as a 64-way set-associative cache and uses MVAs translated by CP15 register 13 (see Address translation) from the ARM9TDMI CPU core. The write buffer can hold up to 16 words of data and four separate addresses. The operations of the DCache and the write buffer are closely connected.

The DCache supports write-through and write-back memory regions, controlled by the C and B bits in each section and page descriptor within the MMU translation tables. For clarity, these bits are called Ctt and Btt in the following text. For details see DCache and write buffer operation.

Each DCache line has two dirty bits, one for the first four words of the line, the other for the last four words, and a single virtual TAG address and valid bit for the entire 8-word line. The physical address from which each line is loaded is stored in the PA TAG RAM and is used when writing modified lines back to memory.

When a store hits in the DCache, if the memory region is write-back, the associated dirty bit is set marking the appropriate half-line as being modified. If the cache line is replaced due to a linefill, or if the line is the target of a DCache clean operation, the dirty bits are used to decide whether the whole, half, or none of the line is written back to memory. The line is written back to the same physical address from which it was loaded, regardless of any changes to the MMU translation tables.

The DCache implements allocate-on-read-miss. Random or round-robin replacement can be selected under software control by the RR bit (CP15 register 1, bit 14). Random replacement is selected at reset. A linefill always loads a complete 8-word line.

Data can also be locked in the DCache so that it cannot be overwritten by a linefill. This operates with a granularity of 1/64 th of the cache, which is 64 words (256 bytes).

All data accesses are subject to MMU permission and translation checks. Data accesses that are aborted by the MMU do not cause linefills or data accesses to appear on the AMBA ASB interface.

For clarity, the C bit (bit 2 in CP15 register 1) is called the Ccr bit throughout the following text.

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