2.3.16. Register 13, FCSE PID register

Register 13 is the Fast Context Switch Extension (FCSE) Process Identifier (PID) register. The FCSE PID register is 0x0 on reset.

Reading from CP15 register 13 returns the value of the FCSE PID. Writing CP15 register 13 updates the FCSE PID to the value in bits [31:25]. Bits [24:0] should be zero.

Register 13 bit assignments are shown in Figure 2.9.

Figure 2.9. Register 13

You can access register 13 using the following instructions:

MRC p15, 0, Rd, c13, c0, 0								;read FCSE PID
MCR p15, 0, Rd, c13, c0, 0								;write FCSE PID

Using the FCSE process identifier (FCSE PID)

Addresses issued by the ARM9TDMI core in the range 0 to 32MB are translated by CP15 register 13, the FCSE PID register. Address A becomes A + (FCSE_PID x 32MB). It is this translated address that is seen by both the caches and MMU. See Processor functional block diagram. Addresses above 32MB undergo no translation. This is shown in Figure 2.10.

The FCSE_PID is a 7-bit field, enabling 128 x 32MB processes to be mapped.

Note

If FCSE_PID is zero, as it is on reset, then there is a flat mapping between the ARM9TDMI and the caches and MMU.

Figure 2.10. Address mapping using CP15 Register 13

Changing the FCSE PID, performing a fast context switch

To do a fast context switch, write to CP15 register 13. The contents of the caches and TLBs do not have to be flushed after a fast context switch because they still hold valid address tags. The two instructions after the MCR to write the FCSE_PID are fetched with the old FCSE_PID value:

{FCSE_PID = 0}
MOV r0, #1:SHL:25				; Fetched with FCSE_PID = 0
MCR p15,0,r0,c13,c0,0				; Fetched with FCSE_PID = 0
A1				; Fetched with FCSE_PID = 0
A2				; Fetched with FCSE_PID = 0
A3				; Fetched with FCSE_PID = 1
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