ARM920T Technical Reference Manual

(Rev 1)

Table of Contents

About this document
Intended audience
Using this manual
Typographical conventions
Timing diagram conventions
Further reading
ARM publications
Other publications
Feedback on the ARM920T
Feedback on the ARM920T Technical Reference Manual
1. Introduction
1.1. About the ARM920T
1.2. Processor functional block diagram
2. Programmer’s Model
2.1. About the programmer’s model
2.2. About the ARM9TDMI programmer’s model
2.2.1. Data Abort model
2.2.2. Instruction set extension spaces
2.3. CP15 register map summary
2.3.1. Addresses in ARM920T
2.3.2. Accessing CP15 registers
2.3.3. Register 0, ID code register
2.3.4. Register 0, cache type register
2.3.5. Register 1, control register
2.3.6. Register 2, translation table base (TTB) register
2.3.7. Register 3, domain access control register
2.3.8. Register 4, reserved
2.3.9. Register 5, fault status registers
2.3.10. Register 6, fault address register
2.3.11. Register 7, cache operations register
2.3.12. Register 8, TLB operations register
2.3.13. Register 9, cache lockdown register
2.3.14. Register 10, TLB lockdown register
2.3.15. Registers 11, 12, and 14, reserved
2.3.16. Register 13, FCSE PID register
2.3.17. Register 15, test configuration register
3. Memory Management Unit
3.1. About the MMU
3.1.1. Access permissions and domains
3.1.2. Translated entries
3.2. MMU program accessible registers
3.3. Address translation
3.3.1. Translation table base
3.3.2. Level one fetch
3.3.3. Level one descriptor
3.3.4. Section descriptor
3.3.5. Coarse page table descriptor
3.3.6. Fine page table descriptor
3.3.7. Translating section references
3.3.8. Level two descriptor
3.3.9. Translating large page references
3.3.10. Translating small page references
3.3.11. Translating tiny page references
3.3.12. Subpages
3.4. MMU faults and CPU aborts
3.5. Fault address and fault status registers
3.5.1. Fault status
3.6. Domain access control
3.7. Fault checking sequence
3.7.1. Alignment fault
3.7.2. Translation fault
3.7.3. Domain fault
3.7.4. Permission fault
3.8. External aborts
3.9. Interaction of the MMU and caches
3.9.1. Enabling the MMU
3.9.2. Disabling the MMU
4. Caches, Write Buffer, and Physical Address TAG (PA TAG) RAM
4.1. About the caches and write buffer
4.2. ICache
4.2.1. ICache organization
4.2.2. Enabling and disabling the ICache
4.2.3. ICache operation
4.2.4. ICache replacement algorithm
4.2.5. ICache lockdown
4.3. DCache and write buffer
4.3.1. Enabling and disabling the DCache and write buffer
4.3.2. DCache and write buffer operation
4.3.3. DCache organization
4.3.4. DCache replacement algorithm
4.3.5. Swap instructions
4.3.6. DCache lockdown
4.4. Cache coherence
4.5. Cache cleaning when lockdown is in use
4.6. Implementation notes
4.7. Physical address TAG RAM
4.8. Drain write buffer
4.9. Wait for interrupt
Clock Modes. Clock Modes
Clock Modes.1. About ARM920T clocking
Clock Modes.2. FastBus mode
Clock Modes.3. Synchronous mode
Clock Modes.4. Asynchronous mode
6. Bus Interface Unit
6.1. About the ARM920T bus interface
6.2. Unidirectional AMBA ASB interface
6.3. Fully-compliant AMBA ASB interface
6.3.1. Connecting the ARM920T to an AMBA ASB interface
6.3.2. Transfer types
6.3.3. Instruction fetch after reset
6.3.4. Noncached LDRs and noncached fetches
6.3.5. Noncached LDM
6.3.6. Buffered and nonbuffered STR
6.3.7. Buffered and nonbuffered STM
6.3.8. Cached LDR, cached LDM, and cached fetch
6.3.9. Dirty data eviction, write-back of 4 or 8 words
6.3.10. Swap
6.3.11. Page walk
6.3.12. AMBA ASB slave transfers
6.4. AMBA AHB interface
6.5. Level 2 cache support and performance analysis
7. Coprocessor Interface
7.1. About the ARM920T coprocessor interface
7.1.1. Internal coprocessors
7.1.2. External coprocessors
7.1.3. Enabling and disabling the external coprocessor interface buses
7.2. LDC/STC
7.2.1. Coprocessor handshake encoding
7.3. MCR/MRC
7.4. Interlocked MCR
7.5. CDP
7.6. Privileged instructions
7.7. Busy-waiting and interrupts
8. Trace Interface Port
8.1. About the ETM interface
9. Debug Support
9.1. About debug
9.2. Debug systems
9.2.1. The debug host
9.2.2. The protocol converter
9.2.3. The ARM920T processor
9.3. Debug interface signals
9.3.1. Entry into debug state on breakpoint
9.3.2. Breakpoints and exceptions
9.3.3. Watchpoints
9.3.4. Watchpoints and exceptions
9.3.5. Debug request
9.3.6. Actions of the ARM920T in debug state
9.4. Scan chains and JTAG interface
9.5. The JTAG state machine
9.5.1. Reset
9.5.2. Pullup resistors
9.5.3. Instruction register
9.5.4. Public instructions
9.6. Test data registers
9.6.1. Bypass register
9.6.2. ARM920T device identification (ID) code register
9.6.3. Instruction register
9.6.4. Scan chain select register
9.6.5. Scan chains 0, 1, 2, and 3
9.6.6. Scan chain 6
9.6.7. Scan chains 4 and 15, the ARM920T memory system
9.7. ARM920T core clocks
9.8. Clock switching during debug
9.9. Clock switching during test
9.10. Determining the core state and system state
9.10.1. Determining the core state
9.10.2. Determining system state
9.10.3. Instructions that can have the SYSSPEED bit set
9.11. Exit from debug state
9.12. The behavior of the program counter during debug
9.12.1. Breakpoint
9.12.2. Watchpoint
9.12.3. Watchpoint with another exception
9.12.4. Watchpoint and breakpoint
9.12.5. Debug request
9.12.6. System speed accesses
9.12.7. Summary of return address calculations
9.13. EmbeddedICE macrocell
9.13.1. Register map
9.13.2. Using the mask registers
9.13.3. Control registers
9.13.4. Debug control register
9.13.5. Debug status register
9.13.6. Vector catch register
9.14. Vector catching
9.15. Single-stepping
9.16. Debug communications channel
9.16.1. Debug comms channel register
9.16.2. Communications using the comms channel
10. TrackingICE
10.1. About TrackingICE
10.2. Timing requirements
10.3. TrackingICE outputs
11. AMBA Test Interface
11.1. About the AMBA test interface
11.2. Entering and exiting AMBA Test
11.3. Functional test
11.3.1. Creating an ARM920T AMBA functional test
11.4. Burst operations
11.5. PA TAG RAM test
11.6. Cache test
11.6.1. Behavior of the cache index pointer in AMBA cache test
11.6.2. RAM read or write
11.6.3. CAM read or write
11.6.4. CAM match, RAM read
11.7. MMU test
11.7.1. Behavior of the TLB Index pointer in AMBA MMU test
11.7.2. Indexing the RAM2 array
12. Instruction Cycle Summary and Interlocks
12.1. About the instruction cycle summary
12.2. Instruction cycle times
12.2.1. Multiplier cycle counts
12.3. Interlocks
13. AC Characteristics
13.1. ARM920T timing diagrams
13.2. ARM920T timing parameters
13.3. Timing definitions for the ARM920T Trace Interface Port
A. Signal Descriptions
A.1. AMBA signals
A.1.1. AMBA bus specification
A.2. Coprocessor interface signals
A.3. JTAG and TAP controller signals
A.4. Debug signals
A.5. Miscellaneous signals
A.6. ARM920T Trace Interface Port signals
B. CP15 Test Registers
B.1. About the test registers
B.2. Test state register
B.2.1. Bit 12, disable DCache streaming
B.2.2. Bit 11, disable ICache streaming
B.2.3. Bit 10, disable DCache linefill
B.2.4. Bit 9, disable ICache linefill
B.2.5. Bits [8:6], disable CP15 register 1, iA and nF
B.2.6. Bit 5, D force noncachable
B.2.7. Bit 4, I force noncachable
B.2.8. Bit 3, MMU test
B.2.9. Bit 2, I miss abort
B.2.10. Bit 1, D miss abort
B.2.11. Bit 0, CP15 interpret mode
B.3. Cache test registers and operations
B.3.1. Addressing the CAM and RAM
B.3.2. Testing the LFSR
B.4. MMU test registers and operations
B.4.1. Addressing the CAM, RAM1, and RAM2
B.5. StrongARM backwards compatibility operations

List of Figures

1. Key to timing diagram conventions
1.1. ARM920T functional block diagram
2.1. CP15 MRC and MCR bit pattern
2.2. Cache type register format
2.3. Dsize and Isize field format
2.4. Register 7 MVA format
2.5. Register 7 index format
2.6. Register 8 MVA format
2.7. Register 9
2.8. Register 10
2.9. Register 13
2.10. Address mapping using CP15 Register 13
3.1. Translation table base register
3.2. Translating page tables
3.3. Accessing translation table level one descriptors
3.4. Level one descriptor
3.5. Section descriptor
3.6. Coarse page table descriptor
3.7. Fine page table descriptor
3.8. Section translation
3.9. Level two descriptor
3.10. Large page translation from a coarse page table
3.11. Small page translation from a coarse page table
3.12. Tiny page translation from a fine page table
3.13. Domain access control register format
3.14. Sequence for checking faults
4.1. Addressing the 16KB ICache
Clock Modes.1. ARM920T clocking
Clock Modes.2. Synchronous mode FCLK to BCLK zero phase delay
Clock Modes.3. Synchronous mode FCLK to BCLK one phase delay
Clock Modes.4. Asynchronous mode FCLK to BCLK zero cycle delay
Clock Modes.5. Asynchronous mode FCLK to BCLK one cycle delay
6.1. Output buffer for bidirectional signals
6.2. Output buffer for unidirectional signals
6.3. Instruction fetch after reset
6.4. Example LDR from address 0x108
6.5. Example LDM of 5 words from 0x108
6.6. Example nonbuffered STR
6.7. Example nonbuffered STM
6.8. Example linefill from 0x100
6.9. Example 4-word data eviction
6.10. Example swap operation
7.1. ARM920T coprocessor clocking
7.2. ARM920T LDC/STC cycle timing
7.3. ARM920T MCR/MRC transfer timing
7.4. ARM920T interlocked MCR
7.5. ARM920T late canceled CDP
7.6. ARM920T privileged instructions
7.7. ARM920T busy waiting and interrupts
9.1. Typical debug system
9.2. Breakpoint timing
9.3. Watchpoint entry with data processing instruction
9.4. Watchpoint entry with branch
9.5. Test access port (TAP) controller state transitions
9.6. External scan chain multiplexor
9.7. Write back physical address format
9.8. Clock switching on entry to debug state
9.9. Debug exit sequence
9.10. Debug state entry
9.11. ARM9TDMI EmbeddedICE macrocell overview
9.12. Watchpoint control register for data comparison
9.13. Watchpoint control register for instruction comparison
9.14. Debug control register
9.15. Debug status register
9.16. Vector catch register
9.17. Debug comms control register
10.1. Using TrackingICE
11.1. AMBA functional test state machine
11.2. Write data format
12.1. Single load interlock timing
12.2. Two cycle load interlock
12.3. LDM interlock
12.4. LDM dependent interlock
13.1. ARM920T FCLK timed coprocessor interface
13.2. ARM920T BCLK timed coprocessor interface
13.3. ARM920T FCLK related signal timing
13.4. ARM920T BCLK related signal timing
13.5. ARM920T SDOUTBS to TDO relationship
13.6. ARM920T nTRST to other signals relationship
13.7. ARM920T JTAG output signal timing
13.8. ARM920T JTAG input signal timing
13.9. ARM920T FCLK related debug output timing
13.10. ARM920T BCLK related debug output timing
13.11. ARM920T TCK related debug output timing
13.12. ARM920T EDBGRQ to DBGRQI relationship
13.13. ARM920T DBGEN to output relationship
13.14. ARM920T BCLK related Trace Interface Port timing
13.15. ARM920T FCLK related Trace Interface Port timing
13.16. ARM920T BnRES timing
13.17. ARM920T ASB slave transfer timing
13.18. ARM920T ASB master transfer timing
13.19. ARM920T ASB master transfer timing
B.1. CP15 MRC and MCR bit pattern
B.2. Rd format, CAM read
B.3. Rd format, CAM write
B.4. Rd format, RAM read
B.5. Rd format, RAM write
B.6. Rd format, CAM match RAM read
B.7. Data format, CAM read
B.8. Data format, RAM read
B.9. Data format, CAM match RAM read
B.10. Rd format, write I or D cache victim and lockdown base
B.11. Rd format, write I or D cache victim
B.12. Rd format, CAM write and data format, CAM read
B.13. Rd format, RAM1 write
B.14. Data format, RAM1 read
B.15. Rd format, RAM2 write and data format, RAM2 read
B.16. Rd format, write I or D TLB lockdown

List of Tables

2.1. ARM9TDMI implementation options
2.2. CP15 register map
2.3. Address types in ARM920T
2.4. CP15 abbreviations
2.5. Register 0, ID code
2.6. Cache type register format
2.7. Cache size encoding (M=0)
2.8. Cache associativity encoding (M=0)
2.9. Line length encoding
2.10. Control register 1 bit functions
2.11. Clocking modes
2.12. Register 2, translation table base
2.13. Register 3, domain access control
2.14. Fault status register
2.15. Function descriptions register 7
2.16. Cache operations register 7
2.17. TLB operations register 8
2.18. Accessing the cache lockdown register 9
2.19. Accessing the TLB lockdown register 10
3.1. CP15 register functions
3.2. Level one descriptor bits
3.3. Interpreting level one descriptor bits [1:0]
3.4. Section descriptor bits
3.5. Coarse page table descriptor bits
3.6. Fine page table descriptor bits
3.7. Level two descriptor bits
3.8. Interpreting page table entry bits [1:0]
3.9. Priority encoding of fault status
3.10. Interpreting access control bits in domain access control register
3.11. Interpreting access permission (AP) bits
4.1. DCache and write buffer configuration
Clock Modes.1. Clock selection for external memory accesses
6.1. Relationship between bidirectional and unidirectional ASB interface
6.2. ARM920T input/output timing
6.3. AMBA ASB transfer types
6.4. Burst transfers
6.5. Use of WRITEOUT signal
6.6. Noncached LDR and fetch
6.7. Data eviction of 4 or 8 words
6.8. ARM920T supported bus access types
7.1. Handshake encoding
9.1. Public instructions
9.2. ID code register
9.3. Scan chain number allocation
9.4. Scan chain 0 bit order
9.5. Scan chain 1 bit function
9.6. Scan chain 2 bit function
9.7. Scan chain 15 format and access modes
9.8. Scan chain 15 physical access mode bit format
9.9. Physical access mapping to CP15 registers
9.10. Scan chain 15 interpreted access mode bit format
9.11. Interpreted access mapping to CP15 registers
9.12. Interpreted access mapping to the MMU
9.13. Interpreted access mapping to the caches
9.14. Scan chain 4 format
9.15. ARM9TDMI EmbeddedICE macrocell register map
9.16. Watchpoint control register, data comparison bit functions
9.17. Watchpoint control register for instruction comparison bit functions
9.18. Debug status register bit functions
9.19. Debug comms control register bit functions
10.1. ARM920T in TrackingICE mode 
11.1. AMBA test modes
11.2. AMBA functional test locations
11.3. Construction of A920Inputs location
11.4. Construction of A920Status1 location
11.5. Construction of A920Status2 location
11.6. Burst locations
11.7. PA TAG RAM locations
11.8. Construction of data pattern write data
11.9. Cache test locations
11.10. CAM write data
11.11. CAM match write data
11.12. CAM match read data
11.13. Invalidate by VA write data
11.14. Lockdown victim and base data
11.15. MMU test locations
11.16. Invalidate by VA data
11.17. Match write data
11.18. CAM data
11.19. CAM data Size_C encoding
11.20. RAM1 data
11.21. RAM1 data access permission bits
11.22. RAM2 data
11.23. RAM2 data Size_R2 encoding
12.1. Symbols used in tables
12.2. Instruction cycle bus times
12.3. Data bus instruction times
13.1. ARM920T timing parameters
13.2. ARM920T Trace Interface Port timing definitions
A.1. AMBA signals
A.2. Coprocessor interface signals
A.3. JTAG and TAP controller signals
A.4. Debug signals
A.5. Miscellaneous signals
A.6. Trace signals
B.1. Test state register
B.2. Clocking mode selection
B.3. Register 7 operations
B.4. Register 9 operations
B.5. Register 15 operations
B.6. CP15 MCR and MRC instructions
B.7. Register 7, 9, and 15 operations
B.8. Write cache victim and lockdown operations
B.9. TTB register operations
B.10. DAC register operations
B.11. FSR register operations
B.12. FAR register operations
B.13. Register 8 operations
B.14. Register 10 operations
B.15. CAM, RAM1, and RAM2 register 15 operations
B.16. Register 2, 3, 5, 6, 8, 10, and 15 operations
B.17. CAM memory region size
B.18. Access permission bit setting
B.19. Miss and fault encoding
B.20. RAM2 memory region size
B.21. Write TLB lockdown operations

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This document is intended only to assist the reader in the use of the product. ARM Limited shall not be liable for any loss or damage arising from the use of any information in this document, or any error or omission in such information, or any incorrect use of the product.

Figure 9.5 reprinted with permission IEEE Std 1149.1-1990, IEEE Standard Test Access Port and Boundary-Scan Architecture Copyright 2000, by IEEE. The IEEE disclaims any responsibility or liability resulting from the placement and use in the described manner

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Product Status

The information in this document is final, that is for a developed product.

Revision History
Revision A31st January 2000First release
Revision B5th September 2000Second release
Revision C18th April 2001Third release
Copyright © 2000, 2001 ARM Limited. All rights reserved.ARM DDI 0151C