2.3.15. Register 15, Test state register

Register 15 gives you access to the test features included within the ARM946E-S. The register is accessed by:

MCR {cond} p15, 0, rd, c15, c0, 0; write test state register
MRC {cond} p15, 0, rd, c15, c0, 0; read test state register

The bit assignments of the test state access register are shown in Table 2.26.

Table 2.26. Test state register bit assignments

Bit

Function

31:13

Unpredictable

12

Disable DCache streaming

11

Disable ICache streaming

10

Disable DCache linefill

9

Disable ICache linefill

8:0

Reserved

Reading the test state register returns bits [12:0] in the least significant bits. The 19 most significant bits are unpredictable. Writing the test state register updates only bits [12:9].

In debug you must be able to execute code without causing linefills to update the caches, primarily to load new code into memory. This means that STRs, if they hit the cache, must update the memory and the cache, and that for LDRs or instruction prefetches that miss, a linefill is not performed. When set, bits [10:9] prevent the respective cache from performing a linefill on a cache miss. The memory mapping, as seen by the ARM9E-S or by the programmer, is unchanged. This improves the performance of single-stepping when in debug.

When set, bits [12:11] prevent the respective cache from streaming data to the ARM9E-S while the linefill is performed to the cache. The linefill still occurs, but the prefetched instruction or load data is returned to the core at the end of a linefill.

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