3.2.2. ICache operation

When enabled, the ICache operation is additionally controlled by the Cachable instruction (Ci) bit stored in the protection unit. This selectively enables or disables caching for different memory regions. The Ci bit affects ICache operation as follows:

Successful cache read

Data is returned to the core only if the Ci bit is 1.

Unsuccessful cache read

If the Ci bit is 1, a linefetch of eight words is performed. The linefetch starts with the requested address aligned to an eight-word boundary (that is, the linefetch starts with word 0). If the Ci bit is 0, a single-word external access is performed to fetch the requested instruction. The cache is not updated.

You can disable the ICache by clearing bit 12 of the CP15 control register. This prevents all ICache look-ups and line fills, and forces all instruction fetches to be performed as single external accesses.

Copyright © 2000 ARM Limited. All rights reserved.ARM DDI 0155A
Non-Confidential