3.2.3. ICache validity

The ARM946E-S does not support external memory snooping. Therefore if you write self-modifying code, the instructions in the ICache can become incoherent with external memory. Similarly, if you reprogram the protection regions, code might exist in the cache that should be in a noncachable region. In either of these cases you must flush the ICache.

You can flush the entire ICache by software in one operation, or you can flush individual cache lines by writing to the CP15 cache operations register (register 7). The ICache is automatically flushed during reset. The ICache never has to be cleaned because its only source of data is from external memory. (The ARM9E-S processor only performs reads from the ICache, except during debug operations.)

Flushing the entire cache

As shown in Table 2.19, you can flush the entire ICache using an MCR instruction. In this case, the contents of the ARM register transferred to CP15 must be zero. You can use the following code segment to do this:

	MOV	r0, #0					; Clear r0
	MCR	p15, r0, c7, c5, 0					; Flush entire instruction cache


The use of r0 is arbitrary.

Flushing the entire cache also flushes any locked-down code. If you want to preserve locked down code, you must flush lines individually, avoiding the locked down lines.

Flushing a single cache line

You can flush single cache lines. To do this, you must specify in Rd the address to be flushed from the cache. You can use the following code segment to do this:

	LDR	r0, =FlushAddress		; Load r0 with address FlushAddress
	MCR	p15, r0, c7, c5, 1			; Flush single cache line
Copyright © 2000 ARM Limited. All rights reserved.ARM DDI 0155A