3.3.1. Enabling and disabling the DCache

You can enable the DCache by setting bit 2 of the CP15 control register. The cache is only enabled if the protection unit is already enabled, or is enabled simultaneously.

You can enable the DCache and protection unit simultaneously with a single write to the CP15 control register, although you must program at least one protection region before you enable the protection unit.

You can disable the DCache by clearing bit2 of the CP15 control register.

The DCache is automatically disabled and flushed on reset.

When the DCache is disabled, cache searches are prevented. This marks all data accesses as noncachable, forcing the ARM946E-S to perform external accesses. The write buffer control is still decoded from the Bd and Cd bits. The Cd bit is forced to 0 (noncachable).

Copyright © 2000 ARM Limited. All rights reserved.ARM DDI 0155A